電流脈波引致次微米金氧半電晶體劣化及防制靜電放電之矽控鎖定

Abstract

當金氧半電晶體受到電壓、電流脈波時，在閘極至汲極重疊區的能帶間穿 透漏電流會增加，這種現象是由於在這個區域中，熱載子引致氧化層電子 被攫取電荷以及產生界面能態。實驗結果顯示Ｎ型金氧半導體的能帶間穿 透漏電流，在起先累增產生區及折回區有增加並分別飽合在某二個值的現 象。我們的實驗觀察揭示現今所存在的Ｎ型金氧半電晶體崩潰模型的不足 ，某些合理的解釋被提出來改進現有的模型，可正確的反應折回現象。此 外，在閘極汲極重疊區的被攫取電子，是現今互補式金氧半導體製程在遭 受低壓靜電放電脈波時的一種新的劣化問題。一個互補式金氧半導體晶片 上靜電放電保護電路被提出及製造，它包含了兩個寄生橫向式矽控整流電 路元件以及兩個低壓觸發元件，來保護Ｎ型及Ｐ型金氧半導體免於正偏或 逆偏靜電放電脈波，我們也在設計時考慮了內部電路。 Increased band-to-band tunneling leakage in the gate-to- drain overlap region due to current or voltage pulses is shown due to hot-carrier induced oxide electron trapped charge andgenerated interface state in this region. Experimental results show that the band-to-band tunneling leakage of NMOSFET is increased and then tends to saturate if it is imposed in the initial avalanche generation or snapback region. Importantly, our experimental observation shows a failure in existing NMOSFET breakdown model. Some plausible interpretations are suggested to improve this model in correctly reflecting the snapback phenomenon. Besides, the trapping charges in the gate-to-drain overlap oxide are new degradation issues in advanced CMOS processes due to low voltage ESD pulses. A CMOS on-chip ESD/ EOS protection circuit is proposed and fabricated, which consists of two parasitic lateral SCR devices and two low voltage trigger elements to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities. We also consider the internal circuits in our design.