次微米互補式金氧半鎖定及基座偏壓產生器

Abstract

本論文主要在探討次微米互補式金氧半的『鎖定效應』，從其物理特性作一通盤性的瞭解，並針對工業界對鎖住電壓提升的渴望著手。因此我們利用半導體元件模擬軟體MEDICI，模擬了各式各樣的結構。在固定製程參數下，改變磊晶層的厚度、n+/p+間的距離、基底偏壓…等，試圖來提升鎖住電壓。 我們也從模擬結果中萃取出鎖定曲線的三區兩點（堵塞區、負電阻區、鎖定區；及激發點、鎖住點）中的各項物理參數來進行分析。並針對鎖住點附近的物理特性類似P-i-n結構，從中推導出鎖住電壓的模型。另外，我們在國際間鎖定的標準量測規範下，建立了一套鎖定的量測系統及量測方法，並對鎖住效應提出一些設計規則。 在基座偏壓產生器方面我們利用電荷幫浦原理，設計並製造出一組可以提供晶片內正╱負偏壓的偏壓產生器。應用於一般的互浦式金氧半晶片上將可大大地提高鎖住電壓。

The essential study of this thesis is on the submicron CMOS latch-up effect. We can draw a general understanding of the physical characteristics of latch-up, with an aim to raise the holding voltage for meeting the industrial requirements, Thus, we utilize the semiconductor device simulator MEDICI to analyze various configurations. Under the fixed process parameters, we change the epitaxial layer thickness, n+/p+ spacing, substrate bias...etc, in order to raise the holding voltage. Further, we separate the latch-up curve into the "three sub-regions/two points" (i.e blocking region, negative resistance region, latched region, triggering point, and holding point), based on the simulation results. Thus various physical parameters can be extracted for study and analysis. In the vicinity of holding point where the physical mechanism is like a p-i-n diode structure, we have derived a holding voltage model. On the other hand, by following the international standard latch-up test guidelines, we set up a latch-up test system and methodology.At the same time, we propose a design rule for latch-up robustness. In substrate bias generator, we utilize charge pumping principle, and design and fabricate a set of bias generator to support on chip a positive or negative bias. Applying it to the CMOS chip will raise the holding voltage efficiently.