數位行動通訊鎖相迴路及等化器之積體電路設計

Abstract

本論文中我們探究數位鎖相迴路DSL及相位等化器。數位鎖相迴路DSL 擁有線性的相位差特徵曲線以及利於分析的特性，而且它的硬體比DTL簡 單。相位等化器是一種利用結果導向相位追蹤的等化器結構。這種等化器 只對相位做運算，不像大多數傳統等化演算法需要的乘法器。所以數位鎖 相迴路DSL及相位等化器將有利於簡化接收端的電路。 我們將此數位 鎖相迴路DSL及相位等化器應用在以PI/4-DQPSK調變的數位汽車電話系統 上。根據電腦模擬的結果顯示，在此系統中合併的數位鎖相迴路DSL及相 位等化器表現的比N-phase DSL好。此外，我們也完成了電路的設計，並 以電路設計程式VERILOG及SYNOPSYS驗證此電路設計的正確性及可行性。 In this thesis, a combined DSL and Phase Equalizer is investigated. The DSL is a nonuniform-sampling DPLL whose phase error detector, using the arcsine function with the quadrature samples of incoming signal, has a linearcharacteristics with a period of 2PI. The Phase Equalizer which uses decision-directed phase tracking method operates on the phase information only. It avoids the multiplication operations required in most conventional equalization algorithm. The application of the combined DSL and Phase Equalizer to the digital cellular radio with PI/4-DQPSK modulation is studied in this thesis.And, afterour simulation, the combined DSL and Phase Equalizer has a better performance in BER than the N-phase DSL system. In addition to the software simulations, the hardware design of the combined DSL and Phase Equalizer is realized in a gate-level. According to the hardware simulation, the circuit design is workable.