2V, 110 MHz, 64 個相位的 CMOS 相鎖迴路

Abstract

本篇論文描述一個 2V, 110 MHz, 64 個相位的 CMOS 相鎖迴路, 它 包含有相位/頻率偵測器, 電荷充放電路, 迴路濾波器, 64 個相位的壓控 振盪器及除頻器. 本系統在此的主要應用是供應相位振幅相量調變器中的 多相位輸入信號. 改良型的多相位壓控振盪器是使用 4 乘 8 的環狀 陣列振盪器的架構, 它可產生 64 個規則排列的精確相位, 且平均分布於 一個週期內, 其解析度是 1/8 個緩衝器延遲時間. 此外這個架構不會有 多重振盪模式出現. 壓控振盪器的輸出頻率範圍重是從 20 MHz 到160 MHz, 中心頻率則為 110MHz. 新型的電流模式相位/頻率偵測器與電荷 充放電路皆比傳統的架構簡單, 且相位/頻率偵測器輸出不會出現 UP 與 DN 輸出信號同時出現的問題. 而電荷充放電路省去了傳統架構中須加入 運算放大器的麻煩, 其輸出電壓可正比於兩時脈輸入的相位差. 除頻器的 除數是 4, 且是同步的架構, 可避免抖動的傳遞. 系統中所有電路皆是電 流模式的, 其信號皆是完全差動信號. 此相鎖迴路系統是使用 0.6 um SPDM CMOS 製程技術下線生產. 電源電壓為 2V, 和向量調變器合在一起 的晶片面積為 2800 * 2800 平方微米. 整個系統 ( 含壓控振盪器 ) 的 最大耗電量為 42 mW. This thesis described the design of a 2V 110 MHz 64-phase CMOS phase-lockedloop (PLL), which is to be used in a phase-magnitude vector modulator. The PLLis consisted of 64-phase voltage- controlled oscillator (VCO), a divide-by-4frequency divider, a phase-frequency detector (PFD), and a charge-pumpingfilter (CP). The VCO is a 4-by-8 array oscillator, that can generate 64 outputs of equally-spaced phases spanning the entire oscillation period. The phase resolution is only 1/8 of a buffer delay. The use of 3-input delay cell ensuressingle operation mode. The output frequency of the VCO can vary from 20 MHZ to160 MHz, and the central frequency is 110 MHz. The PFD｛nd CP circuits used in this PLL are different from the conventionalones. The UP and DN signals of the PFD won't be activated at the same time. TheCP circuit changes its output voltage according the UP and DN signals withoutglitches. The divide-by-4 frequency divider is a synchronous divider, in orderto minimize phase jitter. All the digital circuits are base on the current-modelogic, and the signals are fully differential. The PLL has been fabricated with a 0.6 um SPDM CMOS technology. Total powerconsumption is 42 mW from a single 2V supply.