砷化鎵低雜訊放大器微波單晶積體電路之設計與特性分析

Abstract

利用本實驗室所發表電磁理論,來建立被動元件的電磁等效電路模型的微 波單晶低雜訊放大器已製作完成,並且進行測量及分析。利用電腦輔助軟 體(CAD software)及測量的數據，藉以討論面積有限接地平面對真實電路 的影響.我們試著用最小的接地平面和單一直流電源輸入的方式來 縮小我 們原先設計的電路面積.並用 HP EEsof軟體中的" 設計同步("Design Synchronization")的功能,來檢查電路佈局和模擬電路是否一致。對設計 完成的一級低雜訊放 大器其面積為 1.8×1.5 mm2,達到 12.9 dB 的增益 及小於 3.5dB 的噪音指數,兩級放大器其面積為 3.1×1.7 mm2,達到 23.2 dB 的增益及小於 3.75 dB 的噪音指數。 A Low noise amplifier MMIC has been fabricated by means of the passive EM field model provided by our lab[1]. Now, the chip is tested and analyzed.By application of CAD software and the measured data, we study the interaction between the finite ground planes and the real circuits. We try to achieve the minimum area of the ground planes. The GaAs LNA MMICs thatare improved have the properties of single-end DC power supply, smaller areas (that are 1.8×1.5 mm2 for a one-stage amplifier, 3.1 ×1.7 mm2 for a two-stage amplifier), and lower power dissipation 96 mW (operating current of 24 mA @ 4 V) than the original prototype circuits. As well, the "Design Synchronization" functionof HP EEsof software is utilizedto check the consistency between the schematic circuitsand the final layout circuits. The circuit can achieve 12.9 dB gain and lessthan 3.5 dB noise figure for the one-stage amplifier, 23.2 dB gain and lessthan 3.75dB noise figure for the two-stage amplifier. This paper details the complete consideration of designing a LNA MMIC from deciding thickness of a substrateto measuring the original chips.