一新型電荷幫浦鎖相迴路

Abstract

鎖相迴路是要控制一振盪器，使其輸出訊號的振盪頻率與相位能夠穩定 且快速地追隨著輸入振盪訊號的變化。因此如何來加快鎖相迴路拉進( pull-in)及鎖定(lock-in)的速度，是設計鎖相迴路的一個重要課題。在 電荷幫浦型鎖相迴路中，系統頻寬與反應的速度成正比，很明顯的，要減 少拉進時間，就必須加大系統的頻寬。但系統頻寬的大小與雜訊頻寬的大 小成正比。一個常見的解決方法，就是當系統在拉進狀態時，改變系統參 數，用以增大系統頻寬，以得到較快的反應速度；而進入鎖定範圍後，便 以較小的頻寬作為系統的參數，以避免過大的雜訊進入。有許多不同的方 法來達到這個目的，但這些方法都可能會造成電壓控制振盪器(VCO)輸入 電壓的擺動過大，以致於造成 VCO 和電荷幫浦的過載。在本文我們提出 一個新的電荷幫浦型鎖相迴路，可以將 VCO 之輸入電壓擺動固定，因而 不致造成 VCO 及電荷幫浦的過載，來變化系統參數加快拉進的速度。我 們也附上此電路以實際電路完成的實現方法，並且以李帕諾夫穩定度( Lyaponuv stability)的方法證明此一新的鎖相迴路一定會穩定。最後以 電腦模擬驗證此新的方法確實能加快鎖相迴路的拉進速度。 A phase-locked loop (PLL) is used to control a voltage control oscillator (VCO) such that the frequency and phase of VCO output will follow the input signal quickly and stably. Hence it is important to reduce the pull-in and lock-in time in designing a PLL. In a charge-pump PLL, the bandwidth is proportional to the speed of system response. Obviously, we could increase the system bandwidth to reduce the pull-in time. However, as the system bandwidth increases, the noise bandwidth increases, resulting in large frequency and phase errors of the PLL system. A commonly used method to solve this problem is to increase the system bandwidth for fast response during pull-in state, and to decrease the system bandwidth for small noise bandwidth during lock-in state. This approach can be realized in many ways, but they may make large swing voltage of VCO input, resulting in VCO and charge-pump overload. In this thesis, a new charge-pump PLL is proposed. The proposed charge-pump PLL can reduce the pull-in time and has constant swing voltage of VCO input such that the VCO and charge-pump overload can be avoided. One realization of this new charge-pump PLL is also included. We also use the Lyaponuv stability method to prove the stability of the proposed charge-pump PLL. Finally, computer simulations are used to verify the performance of this new charge-pump PLL.