X86超純量處理機指令擷取器之設計

Abstract

超純量(superscalar)架構是新一代處理機普遍採用來提昇效能的技 術。在X86指令集相容處理機發展至超純量架構時，受限於X86指令變動指 令長度及複雜語意的特性，不易在一個時脈內如同精簡指令集(RISC)處理 機般擷取出多個指令。此論文中，我們設計了一個X86超純量處理機指令 擷取器。用指令擷取器、預先解碼器及第一階指令快取記憶體，來解決 X86指令變動長度問題;用分解X86指令為數個基本指令，來處理複雜語意 的特性。根據這個設計出一個可以提供解碼器每個時脈至多5個X86指令( 且至多8個基本指令)輸出的指令擷取器。設計模擬結果：在0.6 um製程下 的時間延遲模擬預估此指令擷取器可在100MHz的處理機上運作。實驗數據 顯示，我們採用的指令擷取原則(5I:1G4 3S2 1S1)效能比Intel Pentium Pro好58%、比AMD K5好28%。此設計提出X86超純量處理機指令擷取問題的 解決方法。此方法使指令擷取器能提供足夠的指令給執行核心，提昇處理 機整體效能。 Superscalar architecture is a processor design methodology that many newgeneration processors use to increase performance. Due to the characteristics of commplexities of x86 instruction set, when an x86 processor uses superscalar architecture, it is not as easy to fetch multiple instructions in one cycle as in a RISC superscalar processor. In this thesis, we design a fetcher for an x86 superscalar processor. Using a fetcher, a predecoder, and a L1 instruction cache with predeocoded information, variable instruction lengths problem in instruction fetch is solved. By translating x86 instructions into groups of primitive operations, the complex semantics problem can be solved. Finally, we design a fetcher which can supply the decoders with up to five x86 instructions(and up to eight primitive operations). Simulation results show that our fetcherdesign can work at 100MHz using 0.6 um CMOS process and that the fetch rate of our fetch rule (5I:1G4 3S2 1S1) outperforms Intel Pentium Pro by 58% and AMD K5by 28%. We propose the method to solve the instruction fetch problems of an x86superscalar processor. This method can supply sufficient instruction bandwidth to the execution core of an x86 superscalar processor, and the performance of the x86 superscalar processor thus be increased.