標題: 一個 2V , 110MHz 之 CMOS 限制放大器
A 2V , 110MHz CMOS limiting amplifier
作者: 陳林謙
Chen, Li-Chan
吳介琮
Jieh-Tsorng Wu
電子研究所
關鍵字: 限制放大器;訊號強度指示器;limiting amplifier;RSSI
公開日期: 1996
摘要: 本篇論文描述一個 2~V, 110~MHz , 限制放大器 它包含有增益級, 電壓位移取消電路 (offset canceling circuit ) ,接 收到的訊號強度指示器 (Received Signal Strength Indicator, RSSI) 和一個固定 gm 的精確電流源. 整個系統的關鍵性的是要在訊號振幅大量變化時, 依然要維特相位的穩 定, 不能產生 太大的相位失真, 這樣在下一級的解調器才能正確地解出 訊號的內容. 所以增益級 是整個晶片的核心電路, 我們使用了八個相 同的放大電路(稱為核心電路)串連來做 為增益級, 在其它的電路輔助 下, 在核心電路上的每個電晶體都能擁有固定的gm值, 我們就是利用它 的固定 gm 的特性來協助使得相位誤差降到最低. 而電壓位移取消電路是用來避免核心電路在放大時可能會因為有些外來的 雜訊 而在差動輸出兩端產生一電壓位移, 如果不給了清除將會使 核心電路不能正確 的工作. 而接收到的訊號強度指示器則是用來記錄輸入訊號強度的變化, 在傳統的 電路上通 使用類比的訊號來代表, 我們則是利用一簡單的1 bit的類 比數位轉換器來取代傳統 的類比表示法, 這是因為我們的電壓只有兩 伏, 如果使用類比輸出其可觀察的範圍 會很小, 所以改變成數位的輸 出, 但是要另外加一個數位濾波器才能得知真正所要 的結果. 本晶片所用的製程為 TSMC 0.6~$\mu$m SPDM CMOS 的製程, 使用電壓為2 ~V, 中心頻率為 110~Mz , 晶片大小為 1500 um x 1200 um, 整個晶片消耗功率為 23 mW. This thesis describes the design of a 2~V, 110 MHz CMOS limiting amplifier, which consists of a gain stage, a offset canceling circuit, a received signal strength indicator( RSSI), and a winding-swing constant-transconductance bias circuit. The key component is the gain stage which cascode eight the same gain cells, called core cell. Under the other circuits' help, every transistor in the core cell can always keep constant transconductance (gm). We use this character to decrease the phase error, which is the most important for our total performance. The offset canceling circuit used in the gain stage cancel the offset of the difference output of every core cell. If there is one offset in the core cell input/output node, the gain stage won't work correctly. The received signal strength indicator record the change of signal strength. RSSI is implemented by analog signal usually, but we use a one bit digital signal to do this. It is because our power supply is only 2~V. If we use analog signal , the reasonable range is very narrow. We need use a digital filer to analysesthe digital output. The limiting amplifier has been implemented with the TSMC 0.6~$ \mu$m SPDM CMOS technology. Total chip size is $1500~um \times 1200~\mu\mbox{m}^2$, including pads and operate from a single 2~V supply. the center frequency is 110 MHz and total power consumption is 23 mW.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT850428064
http://hdl.handle.net/11536/61933
Appears in Collections:Thesis