深次微米CMOS時間介電崩潰及鎖定之研究

Abstract

本論文主要探討深次微米 CMOS 時間介電崩潰及鎖定. A 部分討論 時間介電崩潰並且把重點放在開發有關本質及模式-B 之氧化矽破壞的模 擬器. B 部分探究 CMOS 鎖定並專注於維持點的模型化. 在 A 部分 ，以 R. Degraeve 等人於 1995 年所做的成果為基礎之下發展出一個 C 語言程式用以模擬極薄二氧化矽的時間介電崩潰分佈. 對於蒙地卡羅方法 的基本概念及一些模擬的參數都將以更詳細討論. 而後，結合 J. C. Lee 等人所提出的二氧化矽變薄之觀念，一個新的想法被提出用以模擬模式-B 之二氧化矽破壞的統計分佈. 在 B 部分保持點的模型化主要以 J. A. Seitchik 等人在1987年考慮基底推出及導電率調變所導出的模型為基 礎，而 CMOS 電路中的寄生 SCR 的內部行為則用二維元件模擬器做完整 的研究. 一個簡潔維持電壓模型在以上兩個結果的幫助得以建立. 接下來 引入一個結構導向的維持電流公式於這模型中，便可產生一個簡潔完的維 持電壓表示式. 最後發展出一個維持點完整模型. 令人感到驚訝的是這完 模型能正確地解釋鎖定的溫度行為，而這些模型都被實驗證無誤. TDDB and latch-up in deep submicron CMOS are studied in this thesis. TDDB is discussed in the Part A with emphasis on developing a simulator for instrinsic and B-mode oxide failures. The Part B investigates CMOS latch-up and concentrates on the modeling of the holding point. In the Part A, a C-language program is developed to simulate the TDDB distribution of ultra- thin oxides based on the work by R. Degraeve et al. in 1995. Basic concepts of Monte-Carlo method and some parameters for the simulation are discussed in more detail. Combining the program with the concept of oxide thinning by J. C. Lee et al., a new idea is proposed to simulate the statistical distribution of B- mode oxide failures. The modeling of the holding point in the Part B is based on a physically-based analytical model considering conductivity modulation and base push-outby J. A. Seitchik et al. in 1987. The internal behavior of parasitic SCR in CMOS circuits is studied completely by a two-dimensional device simulator. With the help of the above two results, a compact model for the holding voltage is constructed. Then incorporating a structure-oriented holding current formula into this model, a compact, closed-form expression for the holding voltage is produced. Finally, a full model for the holding point is developed. It is surprising that the full model can explain the temperature behavior of latch-up very well. Both of the compact and full models are thoroughly judged by experimental results.