低介電常數材料之研究及其在深次微米金屬半導體積體電路之製程整合之研究

Abstract

摘要

隨著積體電路製作技術的大幅成長,元件線寬持續縮減至深次微米,具有高速’高元件`積集度低功率消耗及低成本之ULSI積體電路得以大量生產製造.伴隨著元件尺寸縮減後,後段金屬導線亦需跟隨著微型化且單一層導線已不敷使用,必須建構多層內導線才得以全部連結,除增加製造程序的複雜度外,與元件微型化不同的是,金屬導線傳輸的速度會隨尺寸之縮短而更遲緩,衍生所謂電阻-電容時間延遲(RC delay time);在内連線結構中,使用低介電常數是一可行且克服此一問題的方法之一. 本論文主要探討以化學氣相沉積所生成之低介電質材料之性質及在製程整合之研究.主要探討的低介電質材料包括: Fluorosilicate glass (FSG), Carbon-doped organo-silicate glass(OSG) 及organo-fluorosilicate glass (OFSG);此外,當積體電路製程轉移至銅製程時,需要有銅阻抗層以防止銅擴散至低介電材質;然而由於銅阻抗層的介電常數極高且銅易氧化影響阻抗層的附著性,因此,低介電常數之銅阻抗層及製程整合之控制在本論文中也加以研究. 低介電質薄膜 FSG 在製程整合最大挑戰為氟在鍍膜熱穩定性的問題.實驗得知,覆蓋一層富矽氧化層 (Silicon-rich oxide; SRO) 可有效的防止氟的擴散而造成製程上的問題.同時;我們亦發現提高鍍膜的沉積溫度,利用氮氣電漿 (PE-N2) 對FSG薄膜表面處理及發展兩種不同沉積方式的FSG薄膜當作金屬介電絕緣層,亦可增加製程整合之穩定性. 為有效降低內導線中之電容值,化學氣相沉積之 Carbon-doped organo-silicate glass 介電質薄膜被導入成為新的介電絕緣層.如何得到較低之介電常數及較高之機械性質為製程整合最大的課題.此外,在半導體製程中,熱處理為不可避免的步驟,因此高熱阻抗也為低介電材料必要之條件.吾人發現不同的反應條件可改變沉積膜之結構,以得到較佳的低介電材料性質;使用Ar氣體在沉積環境中當載氣時,能有效提升鍍膜之電性及機械強度.此外,吾人亦利用Diethoxymethylsiliane (DEMS) 來取代目前所用之反應前驅物 Trimethylsilane (3MS); 實驗結果顯示,在薄膜的性質及實際的製程整合結構中, DEMS-based 的低介電質沉積膜有較優良之電性性質,機械強度及熱穩定性,以及在製程整合中之優越性.此外,在此篇論文中也針對DEMS-based 的低介電質沉積膜的性質,結構及最適化之沉積條件作一詳盡之探討. 由於上述所提之低介電質薄膜各有其優劣點,因此吾人亦發展出一種新的介電質薄膜 organo-fluorosilicate glass.係在 Carbon-doped organo silicate galss 沉積過程中加入含氟原子之氣體,此氟原子可取代不穩定的有機團及改變介電質薄膜的化學結構,因而提高了材料之機械性質,穩定性及附著能力. 在銅嵌大馬士革結構中,銅易氧化及擴散至低介電絕緣層中,造成可靠度的問題,因此,銅阻抗層的性質及沉積前的前處理為製程整合最須考慮的要素.實驗得知,利用氨氣電漿 (NH3) 前處理可有效還原銅氧化物,最適化之前處理時間可得較佳之電性性質,增加銅導體與鄰接鍍膜之附著性,以及避免可靠度的失效.此外,為避免整體電容值的升高,低介電材質的銅阻抗層也被提出來取代傳統之氮化矽 (SiN; k=7) 薄膜.實驗結果顯示,以3MS為前驅物所產生之碳氮化矽 (SiCN) 及碳氧化矽 (SiCO) 薄膜可有效降低介電常數至3-5,此直數值與沉積溫度有關;然而,低溫所沉積的這兩種鍍膜有化學及熱穩定的問題,因此,沉積溫度需高於350oC才能滿足為銅阻抗層之需求.

Abstract

As the device dimensions continue to shrink, interconnect delay becomes a limiting factor for increasing circuit device speed. Since interconnect delay is the product of the resistance in metal interconnect and the capacitance between the metal lines, the minimization of the parasitic capacitance and the resistance in interconnect is required. Incorporation of low-dielectric-constant materials in multilevel interconnect can effectively reduce parasitic capacitance, thus decreasing the transmission delay. In this study, several kinds of low-dielectric-constant materials are investigated, including Fluorine-Silicate-Glass (FSG), carbon-doped organo-silicate glass using trimethylsilane (3MS) and Diethoxymethylsilane (DEMS) as precursors. Moreover, the effects of the low-dielectric-constant materials on the integration issue are studied to evaluate the compatibility of low-k materials on semiconductor process. On the other hand, copper (Cu) barrier film is an indispensable layer in Cu dual-damascene fabrication. This layer can increase the effective interconnect capacitance because its dielectric constant can be as high as 7.0 (SiN film). Meanwhile, to prevent Cu from oxidation, which induces reliability fail, the plasma Cu oxide (CuxO) reduction is performed before Cu barrier film deposition. As a result, this integration process control and varying low-dielectric barrier films evaluation were investigated in this work as well. The SIMS data shows that using a cap layer can enhance the thermal stability of FSG and silicon-rich oxide (SRO) is superior to PE-OX in blocking the F diffusion at high temperature and moisture environment. A double interlayer of high-density plasma FSG and SRO have been developed to control fluorine instability for sub-0.18 mm device. On the other hand, the interconnect conditions need further study for robust integration. A higher FSG deposition temperature, PE-N2 plasma treatment on FSG layer, and a stack of HDP-FSG and PE-FSG layer interconnect is proposed to prevent FSG bubble, Al delamination, and interconnect crack. HDP-FSG can fill the gap as small as 0.23 mm gap, which indicates that FSG can be used for the 0.18 mm processes. Moreover, FSG film with a higher deposition temperature can further fill the 0.21 mm gap, which use FSG in process less than 0.18 mm device. In 600Å USG/8000Å FSG/2,000Å SRO cap layered structure, HDP-FSG shows 7.45 to 7.7% line-to-line capacitance reduction and has similar via resistance to that of USG film. Lower dielectric constant as well as higher mechanical strength of plasma enhanced chemical vapor deposition (PE-CVD) low-k films is required for circuit speed and package. Low-k films deposited by PE-CVD using 3MS and oxygen (O2) precursors in Ar carrier gas exhibited the strongly improvement in deposition rate, non-uniformity, leakage current and hardness due to decreasing micro-porous. However, a bit scarification on dielectric constant of the deposited low-k films occurred. On the other hand, The DEMS-based low-k films had a lower dielectric constant, higher hardness and higher chemical and thermal stability than those of the 3MS-based films. From the results of blanket films and four-level interconnect test devices, the DEMS-based films were found to have superior electrical performance than that of the 3MS-based films. Above results clearly reveal that the DEMS-based films are the promising low-k materials in the next technology generation. Additionally, higher heat resistance is necessary to prevent degradation during the interconnect fabrication process. The films deposited from the DEMS precursor at higher temperatures show a lower amount of carbon component and a preference for monomethylated Si atoms relative to lower deposition temperatures and the higher cross-linking bonding due to CHn bridging network, resulting in higher hardness strength and thermally stability. The electrical performance films from DEMS deposited at different temperatures in ILD test structures was provided similar results as blanket films, showing good electrical performance. The composition, bonding configuration, optical, mechanical, electrical properties and thermal stability of SiCOH films using DEMS and O2 as a precursor by PE-CVD method have been investigated in this work. The refractive index of SiCOH increases with increasing deposition temperature yet decreases with increasing oxygen addition to the deposition recipe. The addition of oxygen dramatically enhanced the plasma deposition rate of DEMS. The as-deposited films also show lower the dielectric constant and decreased mechanical hardness and modulus. The effect of which is reduced at higher temperatures. The results can be accounted for by the changes in composition and bonding configuration, as determined from FT-IR and elemental analyses. The low dielectric constant organo-silica-glass (OSG) films deposited by DEMS and O2 is shown to be the most reliable: the dielectric constant are stable even after a heating test at 700oC and a pressure cooler test for 168 h, and superior to other PE-CVD low-k films deposited by other precursors. However, O2 plasma ashing process lead to the dielectric degradation in deposited low-k films during photo-resist removal processing. The nitrogen plasma treatment is proposed to prevent the damage from oxygen attack on the low-k films deposited by DEMS. A new low-k interlayer dielectric material, organofluorosilicate glass (OFSG), has been developed and characterized. The addition of silicon tetrafluoride to a trimethylsilane-based organosilicate glass deposition process provides chemical and structural changes to the deposited film that result in improved mechanical strength at comparable dielectric constants to their non-fluorinated analogs. The presence of SiF4 in the plasma affects the replacement of more labile organic species with 2-3 atomic percent inorganic fluorine, providing enhanced material stability. The chemical and structural changes also result in enhanced adhesive strength and reduced residual stress and stress hysteresis. The resistance of OSG and OFSG films against heat and moisture stress test was investigated. Compared with OSG films, the OFSG films were shown to be having superior thermal stability and electrical properties. The enhanced degradation of the dielectric constant of OFSG films during moisture stress tests was attributed to the hydrolytic instability of Si-F bonds. Consequently, similar to fluorosilicate glass, moisture resistance of the OFSG film will require attention during integration of this material. While various low-k (k ~3.0) materials have been extensively developed as the inter-layer dielectrics (ILDs), high dielectric constant (k ~7.0) silicon nitride (SiN) is still the primary candidate for the Cu capping barrier and etching stop layer required in the Cu dual damascene structure. To further reduce the effective dielectric constant of the Cu interconnects system. In addition, Cu can be easily be oxidized when exposed to commonly used processing environments at low temperatures (<200oC), and such oxidation could negatively impact component performance and reliability. Therefore, Cu oxide (CuxO) should be completely removed by reduction reaction through hydrogen-based plasma treatment to ensure superior conductivity of the Cu interconnects and to enhance the adhesion of SiN to the post Cu-CMP surface. NH3 and H2 plasma pre-treatments have been investigated as a method of removing the oxide from the Cu surface, to improve the adhesion of the PE-CVD barrier layer to post Cu-CMP surfaces. H2 plasma treatment showed an excellent CuxO removal rate and had less impact on the low-dielectric ILD layer. A higher leakage current between Cu lines was the main drawback for this pre-treatment. Insufficient exposure to the NH3 plasma pre-treatment leads to an increased occurrence probability of delamination at the Cu/SiN interface. Optimization of the NH3 treatment time resulted in the reduction of the adhesion failures and a lower metal leakage current. In addition, excessive thermal time (pre-heating and treatment time) induces the Cu-hump problem, resulting in a reliability failure. A longer waiting time (>18 h) leads to delamination at the SiN/Cu surface, even after performing the NH3 treatment. The post Cu-CMP clean seemed to effectively solve this issue, but increased the process complexity. Therefore, optimization of the process time prior to the Cu barrier layer deposition process is crucial for ensuring the performance of the Cu interconnects. SiN and 3MS-based silicon carbide (SiCN and SiCO) films deposited by PE-CVD method have been comprehensively investigated by varying deposition temperature. The important requirements for the Cu barrier layer were adequately considered in terms of these three films. Among these barrier films, PE-SiN films with varying deposition temperature (200-450oC) still were the excellent option as Cu barrier layer film due to the possession of high barrier properties and integration capacitance. In addition, SiN film with low hydrogen content has a superior etch selectivity and a better electrical performance. However, the lethality of this film is higher dielectric constant, as high as 7.0.in the 200-450oC deposition temperature. Therefore, much effort need to done to lower permittivity for the reduction of the parasitic capacitance. On the other hand, a 3MS-based barrier film, including SiCN and SiCO films, can reduce the dielectric constant to 3~5, depends on the deposition temperature. Although the film with lower deposition temperature can further reduce the dielectric constant, it suffers from the predicament of the thermal and chemical stability. As a result, the deposition temperature of the film must above 350oC to improve its properties to have a good fit as Cu barrier layer.