一個2伏特1GHz之CMOS相鎖迴路

Abstract

本篇論文描述一個工作在2伏特1GHz之CMOS相鎖迴路，它包含有： (1)電壓控制振盪器（Voltage Controlled Oscillator）(2)多係數除頻器（Multi-Modulus Divider）(3)相位╱頻率偵測器（Phase-Frequency Detector）(4) 電荷充式濾波器（Charge-Pump Filter）等。此系統是運用於提供射頻前級（RF Front-End）電路的輸入訊號，再與接受天線的射頻訊號混波。 射頻電壓控制振盪器是本論文的核心，由負電阻，蚊香型電感和可調式電容所組成，其中的可調式電容並不是改變介面電容的偏壓，而是由電路設計方法實現。振盪器的輸出頻率範圍從1.13GHz至0.99GHz，表示調頻範圍超過10%。 非同步多係數除頻器可除頻倍數從8到18，最高可除頻率為1.33GHz。相位╱頻率偵測器是比較外部輸入參考信號與內部除頻後信號的相位及頻率差，產生充電Up和放電DN的數位信號。對稱式的電荷充式濾波器則是將相位╱頻率偵測器的數位輸出，轉換成電壓控制振盪器所能接受的類比輸入訊號，以控制振盪器的輸出頻率。當頻率差極大時，可打開電荷充式濾波器中的跳頻電路，使差動輸出訊號增大，以加快改變振盪器的輸出頻率。此外，相位╱頻率偵測器的數位輸出信號，亦提供給電壓控制振盪器，在s-domain分析上造成一個Feed-forward zero，以替代一般的RC-Filter。系統中所有電路架構都是採對稱式的，以產生完全差動信號，而數位電路皆是電流模式，是為了減小電源雜訊的影響。 此相鎖迴路是使用0.6um SPDM CMOS的製程技術製造，電源電壓為2v，包含pads的晶片面積為 2272×2608um2，總消耗功率是58.3mW。

This thesis describes design of 2V 1 GHz CMOS phase-locked loop (PLL), which is composed of a voltage-control oscillator (VCO): a multi-modulus divider (MDIV); a phase-frequency detector (PFD): and a charge-pump filter (CP). The PLL is used in the trequency synthesizer for an RF Front-End. The VCO is an LC-tuned negative-resistance oscillator. Its output frequency can be adjusted by a simulated-varactor circuit, and can be varied from 0.99 GHz to 1.13 GHz. The multi-modulus divider has a frequency divided ratio.varying from 8 to 18. The highest input-frequency of the divider is 1.33GHz. The PFD compares the phase and frequency of the divider output with those of a reference input. The CP receives the Up and DN signals from the PFD. and outputs a differential-analog signals for the VCO. The PFD also connects with the VCO and contributes a feed-forward zero in s-domain. All digital circuits are implemented with current-mode logic to minimize power noise and the signals are fully differential. The PLL has been fabricated with a 0.6um SPDM CMOS technology. The total chip area is 2272× 2608um2 including pads. The total power consumption is 58.3 mW from a single 2V supply.