具有高派發率之超純量微處理機的分離式指令分配單元

Abstract

超純量微處理機的效能受限於保留站(reservation station)的大小。現 今的微處理機藉由增加保留站的大小來提高效能。然而，保留站是相當耗 費硬體的。因為它必須為懸而未決(pending)的運算元(operand)檢查結果 匯流排(result bus)是否有此運算元所需的值。在本篇論文中我們提出分 離式指令分配單元(decoupling instruction dispatch unit)的設計構想 。此分離式指令分配單元內包含分配佇列(dispatcher queue)。分配佇列 以先進先出方式運作，具有較少的硬體花費，並且可以取代一些保留站儲 存格(entry)的分離功能(decoupling function)。分配佇列的硬體成本與 效能分別在本篇論文中有所估計與模擬。實驗結果顯示，一個保留站儲存 格的硬體成本約等於甚或高於四個分配佇列儲存格的硬體成本。模擬結果 顯示使用分配佇列可以增加微處理機的效能。而且，在同樣的硬體成本考 量之下，以相同成本的分配佇列儲存格取代一些保留站儲存格通常可以獲 得比完全使用保留站儲存格較好的效能。其中，以使用四個分配佇列儲存 格取代一個保留站儲存格的效果最好。 The performances of superscalar microprocessors are affected by thenumbers of entries of the reservation stations (RSs). Currently,designers of microprocessors may increase the numbers of entries inthe RSs to achieve higher performance. However, RS entries arehardware consumptive because that they must check the result busesfor pending operands. In this thesis, a decoupling instruction dispatchunit (decoupling dispatcher) is proposed. The dispatcher queues (DQs)of the decoupling dispatcher work as FIFO queues and can replace thedecoupling functions of some RS entries with less cost. Hardware costand performance of the dispatcher queues are evaluated and simulated,respectively. Experimental results show that the hardware cost of an RSentry is about 4 times of that of a DQ entry or even more costly. Simulation results show that the use of DQs can increase performancesof microprocessors. Moreover, under the same hardware cost, performanceof replacing some RS entries with the same cost DQ entries usually achieveshigher performance than no RS entries are replaced. We observe that usingfour DQ entries to replace one RS entry is the best case.