具有位址佇列之x86超純量處理機指令擷取器設計

Abstract

由於指令擷取是微處理器管線中最前端的一級，因此其對於微處理器 的效能有相當大地影響。在超純量微處理器中，指令擷取器每一時脈周期 必須提供數個指令給解碼器。然而在x86架構下，由於不固定長度的指令 集和複雜的定址系統使得在一個時脈週期內要擷取多個指令相當困難。在 此論文中我們設計了一個高頻寬的x86超純量指令擷取器。我們使用預先 解碼的方式達到一個時脈週期內辨識出數個指令並將之送至正確的解碼器 的須求。我們並提出了一個稱為位址佇列的機制以維護指令之位址。此機 制並可降低x86微處理器中線路的複雜度。根據模擬的結果，由於我們的 擷取規則是根據基準程式模擬行為所訂定的，因此我們的設計能穩定地提 供足夠的指令給解碼器。而電路合成結果顯示在相同制程技術下我們的設 計與現有的x86超純量處理器可達到同樣的時脈週期。 Instruction fetch is the first pipeline stage in microprocessors and itinfluences the performance of microprocessors significantly. In a superscalarmicroprocessor, the instruction fetcher must provide multiple instructions tothe decoders each clock cycle. However, in x86 architecture, the variable-length instruction set and the complex addressing system makes fetching multiple instructions in a clock cycle difficult. In this thesis we designed a high-bandwidth instruction fetcher for x86 superscalar environment. Predecode information is used to help identifying multiple instructions in one clockcycle and assigning duplicated instructions to the decoders for decoding. Amechanism called the Address Queue is proposed for maintaining instruction addresses. It simplifies the data routing in x86 microprocessors. Simulationresults showed that because the fetch rule of our design is deduced from the behavior of benchmark programs, our design can provide instruction decoders with sufficient instruction steadily. Synthesis results showed that our design can reach the same clock rate of currently available x86 superscalar microprocessors if the same process technology is used.