高密度電漿蝕刻應用於深次微米元件結構之研究

Abstract

針對二氧化矽的蝕刻而言，提高電漿源功率、CHF3氣體的流量以及降低偏 壓功率均可提高二氧化矽對光阻的蝕刻選擇比。在蝕刻條件最佳化的情況 下，我們成功的開發出小於0.1(m的壕溝及0.15(m接觸窗的蝕刻技術。對 金屬蝕刻而言，在光阻覆蓋面積小於12％或使用電子束微影用的負光阻時 ，會有等向性蝕刻發生。為了獲得非等向性的蝕刻，我們提高偏壓功率並 添加適量的CHF3氣體，並成功的開發出0.18(m鋁金屬線的蝕刻技術。在氧 氣電漿光阻灰化處理時，對金氧半電容所造成損傷的研究中，我們發現暫 態電容－電壓曲線變形及電荷累積崩潰，對時間的變化較對天線面積比敏 感，並呈現二階段式的退化。而當電漿暴露時間小於120秒時，漏電流僅 有微量提升並且在時間到達300秒突然上升。藉由這些結果，我們建立在 金屬蝕刻時對元件造成損傷的研究中，我們針對不同的蝕刻條件探討其元 件退化的機制。藉由提高偏壓功率及降低電漿源功率，元件退化可明顯的 被抑制。依此概念，我們發展出一個兩階段步驟的蝕刻技術，不但可以避 免元件損傷並且不受蝕刻選擇比降低而影響蝕刻結果。我們也發現一個新 的損傷現象，發生於沒有天線結構的金氧半電容靠近孤立的天線導體時， 元件退化程度隨著距離縮短及鄰近孤立天線數量的增加而增加，並且和電 容所在的位置有顯著的相關性。除此之外，當一個具有天線導體的電容靠 近另一個相同結構的電容時，將造成這兩個電容嚴重損傷。在有關電漿導 致損傷對氧化層厚度的關係研究中，我們作了各種電性量測來評估損傷的 變化。當氧化層厚度從6.2nm降到3.8nm時，損傷會逐漸增大，當厚度進一 步縮小到3.0nm時，損傷明顯的改善，我們也建立了一個損傷機制來說明 這些量測到的現象。 In the etching of SiO2 with high density plasma, the selectivity of SiO2 to photoresist has been improved by increasing the source power and the flow rate of CHF3, and decreasing the bias power. With the optimium etching conditions, we have achieved the sub-quarter-micron-meter etching of SiO2. In the etching of aluminum, isotropic etching has been observed on aluminum patterning as overlaid photoresist covers a surface area with a percentage to the etched wafer less than 12% and the negative resist for the electron-beam lithography is used. The etching conditions are optimized by increasing the bias power and the ratio of CHF3 to Cl2/BCl3 etchants. With the optimum recipe, the anisotropic etching of Al patterns as narrow as 0.18mm has been successfully achieved. It is attributed to the sidewall polymerization via the CHF3 additive and the polymer removal from the flat surface via the increasing bias. About the plasma induced damage during O2 plasma ashing, we observed that the quasi-static C-V (QSCV) distortion and Qbd depend on the exposure time rather than the antenna ratio. The QSCV and Qbd show a two stage degradation as the exposure time increases. The leakage current increases slightly for the specimens exposed to the plasma for less than 120 s, and increases considerably for the ones with the exposure time of 300 s. Based on these results, the degradation mechanism of gate oxides under the helicon O2 plasma is established. In the plasma charging damage during aluminum etching, the etching parameters of aluminum in the helicon wave plasma are characterized to elucidate the mechanism of charging damage. By increasing the ion energy and decreasing the plasma density via increase of the bias power and decrease of the source power, respectively, we can significantly reduce charging damage. On the basis of this concept, we develop a two-step etching technique to suppress the charging damage without selectivity loss. Such a high-density plasma etching technique will be very suitable for the formation of high- density, and narrow-line interconnects. We also propose a new damage phenomenon that the electron shading damage occurs for the capacitors without antenna conductor but approaching to a floating antenna. The damages increase with decreasing the distance between the capacitor and the floating antenna and increasing the number of the surrounded floating antenna. They are also strongly dependent on the capacitor site. Furthermore, when the capacitor with the antenna conductor approaches to another one with the same structures, we observed that both capacitors are heavily damaged. For the formation of the high aspect-ratio-interconnect patterns and the high-packing density, which are resulted from the shrink of devices, these will become serious reliability issues. For the plasma induced damages on Ultra-thin Gate Oxide, a number of electrical measurements were carried out to evaluate the plasma induced damages during helicon-O2-Plasma ashing for the gate-oxide thickness scaling down from 6.2nm to 3.0nm. The results indicate that the damages increase as the oxide thickness decreases from 6.2nm to 3.8nm. The damages are significantly improved when the oxide thickness down to 3.0nm. The mechanism is also established to explain these results.