Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress

Abstract

In this work, a metrology was proposed to realize the distribution of fixed oxide trapped charges and grain boundary trapped states. The (continuous-wave green laser crystallization) n-channel thin-film transistors (TFTs) were forced by dc voltage stress, V(G)=V(D). The gate-to-drain capacitance, C(GD) -V(G), with varying frequency of applied small signal was developed. To probe the distribution of these defects, the difference (initial capacitance values minus stressed capacitance values) of C(GD) -V(G) with different frequencies was precisely studied. (C) 2009 American Institute of Physics. [doi:10.1063/1.3275728]