標題: | Charge-Trapping-Induced Parasitic Capacitance and Resistance in SONOS TFTs Under Gate Bias Stress |
作者: | Lin, Chia-Sheng Chen, Ying-Chung Chang, Ting-Chang Jian, Fu-Yen Li, Hung-Wei Chen, Shih-Ching Chuang, Ying-Shao Chen, Te-Chih Tai, Ya-Hsiang Lee, Ming-Hsien Chen, Jim-Shone 光電工程學系 Department of Photonics |
關鍵字: | Capacitance-voltage characteristics;semiconductor device reliability;SONOS devices |
公開日期: | 1-三月-2011 |
摘要: | This letter investigates the charge-trapping-induced parasitic resistance and capacitance in silicon-oxide-nitride-oxide-silicon thin-film transistors under positive and negative dc bias stresses. The results identify a parasitic capacitance in OFF-state C-V curve caused by electrons trapped in the gate insulator near the defined gate region during the positive stress, as well as the depletion induced by those trapped electrons. Meanwhile, the induced depletions in source/drain also degraded the I-V characteristic when the gate bias is larger than the threshold voltage. However, these degradations slightly recover when the trapped electrons are removed after negative bias stress. The electric field in the undefined gate region is also verified by TCAD simulation software. |
URI: | http://dx.doi.org/10.1109/LED.2010.2095819 http://hdl.handle.net/11536/9237 |
ISSN: | 0741-3106 |
DOI: | 10.1109/LED.2010.2095819 |
期刊: | IEEE ELECTRON DEVICE LETTERS |
Volume: | 32 |
Issue: | 3 |
起始頁: | 321 |
結束頁: | 323 |
顯示於類別: | 期刊論文 |