應用於視訊系統之高頻率倍數全數位式鎖相迴路時脈產生器

Abstract

在本論文中，我們提出一個高頻率倍數的全數位式鎖相迴路，此電路可應用於視訊系統中的時脈產生器，其主要功能是接收顯示卡發出的水平同步訊號，並依據使用者設定的螢幕解析度，產生高頻像素時脈來擷取視訊訊號資料，取樣點的穩定度直接影響到顯示畫面的品質，若是像素時脈不穩定，則顯示畫面會閃爍或抖動。因此，如何在高頻率倍數下，產生一個穩定的時脈訊號，是此電路設計的重點。我們使用標準元件庫來設計整個晶片，並利用合成軟體及自動佈局工具實現電路，最後以90奈米1P9M標準CMOS製程來製作晶片。

In this thesis, an all-digital phase-locked loop with large multiplication factor is presented. This circuit can be applied to the video system as a clock generator. It receives the horizontal synchronous signal from the graphics card and then generates a high frequency pixel clock according to the monitor resolution setting to acquire the video signal data. The stability of this sampling clock affects the display image quality directly. If the pixel clock is not stable, the display image will be glittering or jittering. Therefore, how to design a stable clock generator with large multiplication factor is the point of this thesis. This chip is implemented with standard cell library by synthesis and auto place-and-route tools, and realized using 90nm 1P9M standard CMOS process.