高效率的整合AES加密器與解密器之電路設計

Abstract

前瞻加密標準分成加密演算法與解密演算法兩大部分，本篇論文提出一個新的演算法，用來簡化前瞻加密標準中的混行模組，並設計出一套架構整合加解密演算法，降低積體電路的複雜度進而節省硬體成本。此架構共分成四個模組。位元組替換模組：在轉換與反轉換的過程中，共用同一個乘法反元素轉換表。混行模組：一次考量四位元組來計算陣列，共用轉換與反轉換兩個陣列相同的部分。移列模組：透過硬體接線。密鑰擴充模組：利用即時運算架構來替換以記憶體為基礎的架構。本篇論文利用此架構，設計出資料路徑為128位元以及32位元兩種硬體電路，以符合不同的應用需求。前者的特性在於較高的資料總輸出量，而後者的特性在於較低的硬體總閘數。此兩種硬體電路以Verilog HDL來描述，並使用TSMC 0.18um CMOS標準元件庫來合成，對於資料路徑為128位元的硬體電路，其工作頻率為200 MHz，平均資料總輸出量為1.773 Gbits/s，硬體總閘數為29.6K；資料路徑為32位元的硬體電路，其工作頻率為270 MHz，平均資料總輸出量為598 Mbits/s，硬體總閘數為12.8 K。

The algorithm of Advanced Encryption Standard (AES) is divided into encryption and decryption. This paper proposes a new algorithm to simplify MixColumn and Inverse MixColumn of AES and designs hardware architecture to integrate the algorithm of encryption and decryption. This architecture can reduce the hardware complexity and save the cost consumption. It is separated by four modules. SubBytes module－SubBytes and Inverse SubBytes employ one common look-up table only, i.e., multiplicative inverse table. MixColumns module－This module calculates four bytes array per time and shares their operations between transform and inverse transform. ShiftRows module－This module is realized by the hard-wired method. Key Expansion Module－The on-the-fly operation is used to replace the memory-based. Hence, base on the architecture, this paper designs two kinds of hardware, 128-bit datapath and 32-bit datapath, for a specified application. The former is for the purpose of higher data throughput and the latter is for the purpose of lower hardware gate count. Both circuits of hardware were described using Verilog HDL, synthesized by Synopsys with a 0.18um TSMC standard cell library. The simulation results show that a 128-bit datapath of AES circuit can operate at 200MHz and a 32-bit datapath of AES circuit can operate at 270MHz. The former and the latter can be done at a target average throughput of 1.773 Gbits/s and 598 Mbits/s individually. The hardware cost of the former and the latter have the gate count of 29.6 K and 12.8 K individually.