具時域展頻功能的鎖相迴路之設計

Abstract

本論文是詳述一個應用在計算機中央處理器中，內外時脈的介面，具有將晶片內外的時脈之相位鎖定以消除內外脈波的時間延遲，並兼具頻率合成器的功能，可以將內部的時脈倍頻之鎖相環電路的設計。同時為了減少電磁干擾的影響，以符合其既定規格，我們也利用一些數位電路的配合將鎖相迴路的頻譜在時間領域上做小幅的開展，將能量頻譜密度做時間上的平均，使得在總能量不變的情況下，它的頂點值會降下來，達到我們可以接受的範圍。 這個晶片是採用TSMC 0.6 mm SPTM CMOS的製程技術，由國科會晶片製作中心下線製作，晶片所佔的面積為1000 5 1000 mm2 (不含pad )，晶片內部包含二個鎖相環，前一個做為展頻用，後一個做為倍頻用。工作電壓是3.3伏特，輸入時脈頻率是14.318 MHz，根據模擬的結果，內部壓控振盪器的工作頻率分別是：前一之壓控振盪器串接16級的是28.636MHz；後一個之壓控振盪器串接四級的是2~256MHz。

This thesis describes the design of a Phase Locked Loop which is used in CPU to be the interface between external clock and internal clock, with the function of locking the external and internal clock phase to reduce the time delay between them, and also can be a frequency synthesizer to make internal clock multiple times of external clock. For reducing the influence of EMI to meet the regulative specification, we make use of some digital circuits to spread a few percents of PLL frequency spectrum in time domain, thus the peak value of power spectrum density will be lower down to an acceptable level without changing the total energy. This chip is designed using TSMC 0.6 mm SPTM CMOS process. Total die area excluding pad is 1000 5 1000 mm2. There are two PLL inside, the former one is used for spread spectrum, the later one is used for frequency synthesizer. It works under 3.3V power supply and input frequency is 14.318MHz. According to the simulation result, the operating frequency of VCO with 16 stages inside the former PLL is 28.636MHz; and that with 4 stages inside the later PLL is 2~256MHz.