射頻CMOS特性量測與電路模式

Abstract

由於製程技術以及元件設計能力的進展，矽金氧半場效電晶體已經可以成功地應用於射頻電路的製作。隨著趨勢的演進，以金氧半場效電晶體整合射頻與基頻電路將不再是夢想。對操作於1~2GHz低成本、大量生產的行動電話系統，以矽金氧半場效電晶體為製程便成為具有相當有吸引力的選擇。為了縮短設計的時程以及達到要求的性能，無論是在直流、低頻、射頻的範圍內，都必須要有精確的元件特性模型。此外，雜訊也深深影響次微米互補式金氧半場效電晶體高頻電路特性表現。在這篇論文中，我們測量射頻金氧半電晶體直流和高頻的特性；並且建立一個SPICE 模型來準確模擬射頻金氧半電晶體直流和高頻的特性。這是個以BSIM３模型為基礎的SPICE模型，同時加入對基底組抗電路和閘極、源極之間外部的覆蓋電容的修正。 在量測元件高頻特性時，我們發現所量測元件中有一股從閘極到基底的漏電流。因此我們提出一個方法從漏電元件的雜訊參數中粹取元件本質的最小雜訊比。最終引進一組解析方程式來建立射頻金氧半電晶體雜訊特性的模型，並確定S參數和雜訊參數的關連性。

Recent advancement of process technology and device design has allowed Si MOSFET to be applied successfully to RF circuits. As the trend progresses, it will be possible to integrate RF circuits with base band CMOS circuits. Si MOSFET thus become attractive candidates for low cost, high volume mobile phone systems operating at 1 to 2 GHz. To shorten the design cycle and ensure required circuit performance, an accurate device model for D.C., low frequency and R.F. range is needed. Besides, noises also limit the high frequency performance of submicron CMOS circuit. In this thesis, we measure both the RFCMOS DC and high frequency characteristics and establish a precise SPICE model to simulate both DC and AC characteristics. This SPICE model is based on the BSIM3 model and modifies the substrate resistance network and extrinsic gate-drain overlap capacitance. As we measure the RF characteristics of the test device, A gate to source leakage path is found in our test device. Therefore, we propose a method to evaluate the minimum noise figure of the intrinsic device from the noise parameters of the device with a lakage path. Finally, a set of analytic equations, which is based on long time studies of the microwave noise behavior of MESFETs, is introduced for the RFCMOS noise parameter prediction.