於 CMOS細胞單元電路之雜波傳播及處理雜波之時序模型

Abstract

在深次微米積體電路中，串音，雜波，的發生將更為頻繁。本論文研究雜波如何在CMOS電路中傳播，並提出細胞單元時序模型來描述雜波的傳播。首先我們分析雜波之最小幅度及時間，與邏輯閘之傳播延遲時間的關係。並且，當一邏輯閘的輸入端，其一為雜波而另一為邊緣信號，或是輸入均為雜波時的傳播條件也予以研究。基於以上分析的結果，一個以細胞單元電路為主，並包含雜波的時序模型將被提出。藉此時序模型來推導一簡單例子所得的結果，發現與SPICE模擬的結果相當接近。

In the deep submicron ULSI digital circuit, the coupling noise, spike, appears very often. This thesis studies how the spike can propagate through a CMOS circuit and proposes a cell-based timing model to describe this spike propagation. At first, it analyzes the relationship between the minimum duration and the amplitude of a spike with the propagation delay of a gate in order to propagate the spike. Also the condition of propagating a spike through a gate when it arrives at the gate with an edge or another spike is studied. Based on the results, a cell-based timing model which considers spikes is proposed. A simple example is given to derive the output response by utilizing this model and the result is in agreement with that obtained from the SPICE simulation.