超純量多重處理中推測性記憶體存取技術之研究

Abstract

超純量多重處理系統可以同時開發程式中的粗顆粒及細顆粒平行度來提昇整體系統效能。然而日益擴大的處理器與記憶體速度差將漸漸抵消超純量多重處理系統中平行度的開發。為解決記憶體延遲問題，雖然已有許多方法被提出。諸如：多線處理架構、放寬的記憶體一致模式、及資料預取等等。不過另外一方面在超純量處理中，推測性執行除了可以開發指令平行度外，也可以用來隱藏記憶體延遲。然而在超純量多重處理系統中，為保證程式執行的正確性，超純量處理的動態排程必須遵行特定的記憶體一致模式，因此指令平行度開發及記憶體延遲隱藏都會受到限制。為打破記憶體一致模式的制約，推測性記憶體存取是個相當重要的技術。 本論文在於探討超純量多重處理中推測性記憶體存取技術之設計。首先為能精確地模擬超純量多重處理系統，我們發展了一個超純量多重處理模擬器，此模擬器稱為 smint。藉由此模擬器，我們探討了超純量及多重處理系統中平行度的開發。從模擬結果我們發現藉由中度的超純量處理和高度的多重處理便可完全開發程式中的平行度。接著以此平行度的衡量結果，我探討推測性記憶體存取技術的設計。推測性取出可以隱藏部份的記憶體存取延遲，然而過早的推測性取出易造成錯誤。因此，我們提出了推測性存入技術。由於存入動作會覆蓋記憶體資料，為使推測性存入可回復，我們設計了可回復的推測性存入快取記憶體，同時我們也設計了一個支援前視資料傳輸的快取記憶體一致性規約來實現處理機間的推測性通訊。 藉由此論文的研究，我們發展了一個超純量多重處理模擬器，探討了超存量多重處理系統中平行度的開發，並提出了推測性存入技術。期望此研究結果能對超純量多重處理系統的發展有所助益。

Superscalar multiprocessors can exploit both coarse-grained and fine-grained parallelism in programs. But the continuing widening gap between processor and memory speeds can quickly offset any performance gains expected from the parallelism exploitation of superscalar processing and multiprocessing. To solve the memory latency problem, there have been several mechanisms, such as multithreading, relaxed memory consistency, and data prefetching, proposed. On the other hand, in superscalar processing, speculative execution not only exploits instruction-level parallelism but also hides memory latencies. However, to guarantee correct program execution, the dynamic scheduling capabilities of superscalar processors should be restrict to the access constraints under certain memory consistency models in the superscalar multiprocessor system. As a result, parallelism exploitation and latency hiding may be severe constrained. To break the constraints, speculative memory accesses are vital in superscalar multiprocessing. In this dissertation, we investigate speculative memory access techniques in superscalar multiprocessing. First, in order to enable accurate simulation of multiprocessing systems, we developed a simulator, called SMINT, for superscalar multiprocessing systems. With this simulator, we examined the exploitable parallelism in superscalar processing and multiprocessing. We found that the parallelism in programs can best be exploited with a moderate degree of superscalar processing and a high degree of multiprocessing. Based on the measurement of parallelism, we considered the load/store unit design for superscalar processors to support speculative memory access techniques. Finally, we investigated the memory design issues for speculative memory accesses in superscalar multiprocessing. Previous research shown speculation of load instructions may hide memory access latencies, but early speculation is likely to fail. To increase the success rate of speculative loads, speculation of store instructions is beneficial. While store instructions are destructive to the memory system. To support speculative store, we use speculative write cache and design a new cache coherence protocol to support cache-to-cache lookahead data transfer and reduce interprocessor communication latencies. Through the investigation of this dissertation, we built a superscalar multiprocessor simulator, investigated the parallelism exploitation in superscalar mulitprocessing, and developed the speculative store technique. We hope this research can contribute to the exploitation of parallelism in multiprocessing systems.