於邊界掃描環境下使用振盪源之延遲障礙測試方法與架構

Abstract

系統晶片的測試日漸困難，測試成本也日益增加，若欲進行系統晶片內部的一般組合邏輯電路模組之延遲障礙測試是不易達成的。另外邊界掃描測試已是一普遍所使用的標準測試架構，本論文擬提出一可以藉由改進後的邊界掃描來測試內部模組之延遲障礙。這是結合振盪源測試及邊界掃描測試的測試方法，主要是由輸入端輸入一與該模組之最長延遲時間同樣工作周期之周期性振盪訊號，並以相同之訊息為其取樣控制訊號，再辨識其輸出是否有及時改變。繼而提出一個概念性的測試架構，其主要元件有振盪源（亦可用系統時脈）、可隨機選取輸入端及輸出端的邊界掃描、延遲測試所需的輸入訊息處理器及轉向感測器。我們使用此架構針對一些標準測試電路進行模擬，以及探討在實際應用上，時脈移位對此系統正常運作的影響程度之實質問題。再者，我們以此架構來模擬振盪源之圖樣的產生，並分析其整體成效。

Delay fault testing in system-on-chip is difficult and the cost becomes increasingly higher. Boundary-scan is a standard and commonly used test scheme for ICs. In this thesis, we propose a test scheme to test the delay fault within the system-on-chip by using a modified boundary-scan structure. The main idea of this testing scheme is to provide an oscillation signal with the pulse width equal to the circuit maximum delay length and to observe the output transition before the next transition comes. This test architecture includes: an oscillation source generator (socillator), which could also be the system clock; a modified boundary-scan cell which can be randomly accessed from a primary-input and a primary-output from which we wish to apply tests, and a detector. We applied this scheme to some benchmark circuits and discuss the clock skew problem in practical applications. Furthermore, simulation and analysis on pattern generation for socillator test is done with this scheme. 1.1 The challenge on System-on-chip testing 1.2 Brief introduction to delay fault, socillator test, and boundary-scan 1.3 Previous work on delay fault testing 1.4 The objective of our test scheme 1.5 Overview of thesis Chapter 2 Methodology 2.1 Traditional delay fault testing and measurement 2.2 Path selection 2.3 Input pattern generation for the circuit specification 2.4 Syndrome detection Chapter 3 Architecture 3.1 A global picture 3.2 Boundary-scan cell for primary-input 3.3 Boundary-scan cell for primary-output 3.4 Programmable oscillation ring 3.5 1st pulse eliminator 3.6 Transition detector 3.7 Test flow Chapter 4 Simulation 4.1 Some cases from the simulation results 4.2 Clock skew problem Chapter 5 Test Pattern Generation for Socillator Test Chapter 6 Conclusion