利用振盪源測試來偵測位於數位電路中的藕合障礙

Abstract

隨著深次微米積體電路技術的進步，電路中出現藕合雜訊的頻率是愈來愈高。當電路中的時脈頻率己經超過1 GHz且線與線間的寬度也小於0.15um，一些不可預期的串音效應開始影嚮整個電路的效能。所以要如何在電路設計完成後測電路中所有的障礙是很重要的課題。但不幸地是，傳統的藕合障礙偵測方法並無法保障偵測出所有的藕合障礙。本論文將研究如何利用振盪源測試來偵測所有的藕合障礙，而且發展了一個適用於藕合障擬的障礙模擬程式，及一個利用此種方法來產生測試圖樣的圖樣產生器。這二個程式皆會用幾個標準的電路來測試並估算其效能。

In the deep sub-micron VLSI digital circuit, the coupling noise appears very often. As the clock speed of the IC increases over 1 GHz and the metal line spacings is narrower than 0.15um, unexpected crosstalk effects start to degrade the circuit performance significantly. It is important for the designers to test the faults before taping out the designs. Unfortunately, conventional tests for detecting coupling faults are not guaranteed to detect some potential coupling faults. This thesis studies how to detect all of the coupling faults efficiently using socillator test and also develops a fault simulator which maximizes the number of detected faults under a test pattern and a deterministic test pattern generator to detect coupling faults. In the thesis, at first, the socillator test for detecting coupling faults is described and verified. Then, the algorithm of the fault simulator is discussed and investigated, and a example is given to demonstrate the algorithm. Next, the deterministic pattern generator for detecting coupling faults by forming a sensitized path passing the affecting and victim line is described. For both the above simulator and test generators, they were applied to benchmark circuits to show their effectiveness. Abstract (in English) ………………………………………………………………Ⅱ Chapter 1 Introduction………………………………………………………………..1 1.1 Technology Trend …………………………………………………………..1 1.2 Coupling Effects in Deep Sub-Micron Digital Circuits……………………..2 1.3 Issues of Coupling Fault Testing ……………………………………………3 1.4 Outline of this thesis …………………………………………………………5 Chapter 2 Socillator Test□ An oscillation source test methodology to detect coupling faults ………………………………………………………………………..6 2.1 Previous Work ……………………………………………………………….6 2.2 Socillator Test □ Oscillation Source Test to Detect Coupling Fault ………..7 2.3 Simulation Waveform ……………………………………………………….9 2.4 Test Configuration and A Simple Example ………………………………..10 Chapter 3 A Fault Simulator for Coupling Faults …………………………………..13 3.1 Sensitized Path Graph ……………………………………………………..13 3.2 Line Identification …………………………………………………………14 3.3 Classification of Identified Lines …………………………………………..15 3.4 Fault Set Construction …………………………………………………… 17 3.4.1 Fault Set Construction Procedure for Type 4 Pairs …………………18 3.4.2 Concept of the Algorithm …………………………………………..20 3.5 Program Implementation …………………………………………………..23 3.5.1 Basic Data Structure ………………………………………………..23 3.5.2 Main Function of the Program ……………………………………..24 Chapter 4 Deterministic Test Pattern Generation …………………………………..26 4.1 Sensitized Path …………………………………………………………….26 4.2 Mechanism of the Program ……………………………………………….29 4.2.1 Main Procedure ……………………………………………………29 4.2.2 Test Generation Procedure …………………………………………30 4.2.3 The PODEM like Procedure ……………………………………….32 4.2.4 Backtrace Procedure ……………………………………………….32 4.2.5 Imply Procedure ……………………………………………………33 4.3 An Example ……………………………………………………………….34 4.4 Advantage of this Methodology …………………………………………..35 Chapter 5 Simulation Results and Discussion ……………………………………..36 Chapter 6 Conclusion ………………………………………………………………39