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dc.contributor.author周儒明en_US
dc.contributor.authorJu-Ming Chouen_US
dc.contributor.author吳介琮en_US
dc.contributor.authorJieh-Tsorng Wuen_US
dc.date.accessioned2014-12-12T02:23:12Z-
dc.date.available2014-12-12T02:23:12Z-
dc.date.issued1999en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT880428066en_US
dc.identifier.urihttp://hdl.handle.net/11536/65705-
dc.description.abstract本論文描述一個工作在 3 伏特, 每秒能夠傳輸 9 兆位元的 CMOS 多工器. 它主要包含三個部分: (1)時脈倍頻路徑 (Frequency Multiplier Path), (2)十八對一多工器 (18 to 1 Multiplexer), (3)十八個相位的相鎖迴路時脈產生器 (18 Phase Phase-lock-loop Clock Generator). 此 CMOS 多工器主要應用於高速串列傳輸系統中的發射端, 利用十八對一多工器的功能, 把十八個位元的並列資料轉換為串列資料, 再傳送出去. 為了使 CMOS 多工器能夠達到高速傳輸速率的要求, 本論文以多級結構的方式實現十八對一多工器電路, 其基本構成元件為簡單的二對一多工器與三對一多工器, 此多級結構可克服單級十八對一多工器電路可能造成輸出電容過大的問題. 在時脈產生路徑方面, 捨棄舊式必須使用能產生系統所需最高時脈頻率之相鎖迴路時脈產生器的時脈除頻路徑, 提出一新式的時脈倍頻路徑, 藉由相位摺疊器可使頻率倍增的功能, 使得時脈倍頻路徑僅需使用可產生系統所需最低時脈頻率的相鎖迴路時脈產生器, 即可製作出系統所需的各式時脈頻率與相位, 如此一來便可減低相鎖迴路時脈產生器在製作上的困難度. 在時脈相位的精確度上, 本論文提出一新式的相位平均化電路技術, 藉由在時脈倍頻路徑上加入相位平均化電路, 使得延遲單元或電晶體不匹配所造成的相位偏移量能因相位平均化電阻環圈的相位平均化效果而減小. 本論文使用 0.35um 1P4M CMOS 製程技術進行模擬動作, 電源電壓 為 3 伏特, 消耗功率約 2.5 瓦.zh_TW
dc.description.abstractThis thesis described the design of a 3V CMOS Multiplexer that transmits 9 gigabit per second, which is composed of a frequency multiplier path, an 18 to 1 multiplexer, an 18 phase phase-lock-loop (PLL) clock generator. This CMOS Multiplexer is applied to a transmitter in the high-speed serial link, which converts parallel data into serial data. To achieve the need for high speed, we decide to partitioning the 18 to 1 multiplexer into multi-stage. By designing the 18 to 1 multiplexer composed of one 2 to 1 multiplexer and eight 3 to 1 multiplexers, we could overcome the problem of big output capacitance of single-stage 18 to 1 multiplexer. On clock generation path, we propose a new frequency multiplier path to take the place of old frequency divider path. Old frequency divider path must use the PLL that could generate the fastest frequency of system specification. By the function of phase folder, frequency multiplier path just need the PLL that could generate the slowest frequency of system specification, so we could reduce the degree of difficulty of designing PLL. To reducing the effect of unequal distance between phase that caused by mismatch, we propose a new averaging conception to solve it. By inserting phase averaging resistance ring into frequency multiplier path, we could correlate every phase between phase that angle of phase close to it. Based on the reciprocal influence between phase, we could reduce the effect of phase shift and make the quality of clock of frequency multiplier path better. The CMOS Multiplexer has been simulated with a 0.35um 1P4M CMOS technology. Total power consumption is about 2.5 W under a 3 V supply. 英文摘要 誌謝 表目錄 圖目錄 1 緒論 1.1 研究動機 1.2 論文組織 2 相位平均化電阻環圈 2.1 簡介 2.2 相位不精確的成因 2.3 相位平均化電阻環圈介紹 2.4 相位平均化電阻環圈動作原理 2.5 相位平均化電阻環圈的相位平均化能力探討 2.6 相位平均化緩衝器電路設計 2.7 結論 3 時脈倍頻路徑 3.1 簡介 3.2 相位摺疊器介紹 3.3 相位摺疊器動作原理 3.4 倍頻倍率為三的相位摺疊器設計 3.5 時脈倍頻路徑結構介紹 3.6 結論 4 十八對一多工器 4.1 簡介 4.2 十八對一多工器結構描述 4.3 十八對一多工器之時序分析 4.4 十八對一多工器結構電路設計 4.5 結論 5 十八個相位的相鎖迴路時脈產生器 5.1 簡介 5.2 相鎖迴路時脈產生器的抖動分析 5.3 十八個相位的壓控振盪器設計 5.4 相位/頻率偵測器設計 5.5 電荷充放電路設計 5.6 除頻器設計 5.7 濾波器設計及系統參數 6 結論與建議 6.1 總結 6.2 建議將來研究方向 參考文獻 自傳en_US
dc.language.isozh_TWen_US
dc.subject相位平均化zh_TW
dc.subject相位摺疊器zh_TW
dc.subject鎖相迴路zh_TW
dc.subject時脈倍頻zh_TW
dc.subject發射器zh_TW
dc.subject多工器zh_TW
dc.subjectPhase Averagingen_US
dc.subjectPhase Folderen_US
dc.subjectPhase-lock-loopen_US
dc.subjectFrequency Multiplieren_US
dc.subjectTransmitteren_US
dc.subjectMultiplexeren_US
dc.title3V 9Gbps CMOS 多工器zh_TW
dc.titleA 3V 9Gbps CMOS Multiplexeren_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis