含鉿之閘極介電層於鍺基板之電物性研究

Abstract

本論文中，我們有系統地調查各種含金屬鉿之閘極介電材料，包括二氧化鉿、氮氧化鉿及氮氧化矽鉿，沉積在塊材鍺基板上的電物性研究。 對於鍺晶圓的濕式化學清潔，發現當降低蝕刻酸的濃度時，可以獲得較平坦的鍺表面，但同時亦會失去恐水性的特性。其中最佳化的清潔方式為使用稀釋的氫氟酸(氫氟酸:超純水=1:30)與水作循環式交替沖洗，其均方根表面平整度可達到約0.133 nm。隨著暴露時間的增加，在鍺表面的原生氧化層厚度跟碳污染程度均會增高。除此之外，不管是在氬氣或氮氣氣氛底下，經過五百度熱退火處理後，二氧化鍺的熱脫附現象使得厚度隨著熱退火時間增加而變薄，這些結果都顯示出二氧化鍺的低熱穩定性將可能造成高介電金屬氧化物沉積在鍺積板上的後續製程溫度受到限制以及介面受損的可能性。 由有機金屬化學氣象沉積系統所製備的二氧化鉿薄膜，明顯具有較大的等效氧化層厚度及遲滯現象；經過氮氣的沉積後熱退火處理，即使是四百度的低溫，也會造成電容特性的受損跟漏電流的增加。在沉積二氧化鉿的過程當中，可以得知較低溫的四百度有利於得到較平整的表面及較小的電容遲滯，相對地，較高溫的五百度則呈現相反的情況。另外如果預先疊上金屬鉿(約10 Å)將更進一步造成等效氧化層厚度下降及遲滯增加，但是這個現象只有在五百度的沉積溫度才看得到。其次，二氧化鉿介電層可以透過疊在經過氨氣作氮化處理的鍺表面，獲得更佳的電特性改善。 對於使用濺鍍方式沉積的氮氧化鉿薄膜，隨著熱退火溫度的升高跟時間的延長，得到的等效氧化層厚度皆會下降，但也同時導致遲滯的增加。經過六百度五分鐘的熱退火處理，除了等效氧化層厚度可以降低到19.5 Å，漏電相較比起標準的二氧化矽/矽結構低了四個數量級。然而不幸地，從介電層崩潰對時間相依性的可靠度測試中，我們發現十年生命期隨著熱退火溫度的上升而縮短，推測原因是由於較嚴重的載子捕捉。另一個值得注意的現象是對於剛沉積的氮化鉿薄膜中，即已經出現了不均勻的氧化，但經過後續的高溫製程處理將轉變成為均勻的氮氧化鉿薄膜。此時，當熱退火溫度高於五百度時，我們注意到有大量鍺原子跑入介電層的情況以及氧化鍺的形成。相信透過製程修正的方式可以持續最佳化其接面結構，進而改善氮氧化鉿堆疊在鍺基板的電特性表現，使得氮氧化鉿可以成為未來鍺元件的閘極介電層人選之一。

In this thesis, we have systematically investigated the electrical and material characteristics of hafnium-family gate dielectrics, including HfO2, HfOxNy and HfSiON, on bulk Ge substrates. For wet-chemical cleaning of bulk Ge wafers, the flatter surface morphology is observed with decreasing the acid etching concentration, and the hydrophobic phenomenon is simultaneously disappeared. The optimized surface roughness is ~0.113 nm after the cyclical rinse of diluted HF/D.I. water (1:30) and D.I. water. The growth of native oxide and carbon contamination on Ge surface are characterized with increasing the exposure time. Besides, thermal desorption of GeO2 film is observed after 500°C annealing in Ar and N2 ambient. These findings suggest that the limited processing temperature and the interface damage are probable for high-k metal oxides on Ge due to thermal instability of the GeO2. The as-deposited HfO2 thin film prepared by MOCVD shows the large EOT and hysteresis width. After the N2 post-deposition-annealing (PDA), even for low temperature of 400°C, not only the distortion of C-V curves but also the large gate leakage current have been found. During the HfO2 deposition, the low deposition temperature of 400°C facilitates to obtain smoother film, smaller hysteresis but a larger leakage current, while the high deposition temperature of 500°C presents the opposite tendency. Moreover, the Hf pre-deposition (~10 Å) further reveals the EOT and hysteresis damages only for 500°C. The improved electrical properties of the HfO2 dielectrics are seen on NH3-nitrided Ge surfaces. For sputtered HfOxNy thin film, the EOT decreases with increasing the PDA temperature and time, whereas the hysteresis width is increased. A lower EOT of 19.5 Å with the Jg of 1.8 x 10-5 A/cm2 @ Vg = -1 V, which is ~4 orders reduction as compared to the standard SiO2/Si, has been achieved after 600°C PDA for 5 min. Unfortunately, the 10-year lifetime obtained from the TDDB test is deteriorated with the annealing temperature going up perhaps due to the severe charge trapping. Another noteworthy feature is that the inhomogeneous oxidation of as-deposited HfN film is examined and transferred into the homogeneous HfOxNy film after thermal annealing. Meanwhile, a significant Ge incorporation and the presence of GeOx oxide are also detected upon 500°C. The continuous optimization of the interface structure through process modification has expected to further improve the electrical performance of the HfOxNy/Ge gate stack, which is considered as a candidate for gate dielectric of Ge device.