高介電常數氧化鐠閘極介電層與新穎結構於複晶矽薄膜電晶體之研究

Abstract

此論文提出多種有效方式來改善複晶矽薄膜電晶體的電性，首先，提出具有高介電常數氧化鐠閘極介電層之固相再結晶複晶矽薄膜電晶體。此外，深入探討應用兩種氟鈍化技術包括氟離子佈值及四氟化碳電漿處理以製備高效能及高可靠度之複晶矽氧化鐠薄膜電晶體。並研究兩種複晶矽晶粒尺寸增大技術於固相再結晶複晶矽薄膜電晶體之應用。最後，發展一個簡單的側壁邊襯技術來製作具有奈米線通道之固相結晶和金屬誘發側向結晶複晶矽薄膜電晶體。 首先，整合氮化鈦金屬閘極和高介電常數氧化鐠閘極介電層來發展高效能之固相再結晶複晶矽薄膜電晶體。應用氧化鐠閘極介電層可得到薄的等效氧化層厚度和高的閘極電容密度並且可以使複晶矽通道區域誘發產生更大量的可移動載子。因此，複晶矽薄膜裡的晶粒邊界缺陷態位會被大量誘導產生的載子迅速的填滿，可以大幅的改善次臨界斜率。即使在沒有額外施加氫化處理製程或採用先進的相結晶技術之下，複晶矽氧化鐠閘極介電層薄膜電晶體的電性明顯地勝過傳統的複晶矽氧化矽閘極介電層薄膜電晶體。 接著，我們應用兩種氟鈍化技術包括氟離子佈值及四氟化碳電漿處理於複晶矽氧化鐠閘極介電層薄膜電晶體。這些氟鈍化技術可將氟原子引進複晶矽薄膜中及氧化鐠閘極介電極/複晶矽通道界面處來修補晶粒邊界缺陷態位。因此，藉著摻雜氟原子進入複晶矽薄膜中，複晶矽氧化鐠閘極介電層薄膜電晶體的元件電性以及臨界電壓下降特性可大幅的改善，尤其是針對關閉狀態的漏電流改善更加顯著。此外，這些氟鈍化技術也可形成強的矽-氟鍵結以取代一般弱的矽-矽鍵結以及矽-氫鍵結，以增進熱載子應力的免疫力。 其次，我們發展出兩種具有表面成核固相再結晶方式之複晶矽晶粒尺寸增大技術，其中包括氬離子佈植於非晶矽/下層氧化矽界面處以及新穎的懸浮通道結構。在界面處的大量矽晶粒成核機制可被有效抑制住，而成核機制會選擇由較少成核點的非晶矽自由表面處開始，在較少的矽晶粒成核點情況下可以得到較好的複晶矽晶粒特性包含較大晶粒尺寸及較少結構缺陷。因此，利用這些晶粒尺寸增大技術可以顯著的改善複晶矽薄膜電晶體的電性。 在論文的最後，我們發展出利用簡單的側壁邊襯技術且不需要先進的微影製程來形成自我對準的50奈米線寬的奈米線通道。探討應用固相再結晶和金屬誘發側向再結晶技術於複晶矽奈米線通道薄膜電晶體的應用。由於固相再結晶複晶矽奈米線通道薄膜電晶體具有三維之類三閘極結構，邊際電場會誘導側壁及角落產生額外的電流貢獻效應以增進閘極對奈米線通道的控制能力。另一方面，金屬誘發側向再結晶複晶矽奈米線通道薄膜電晶體具有較佳的複晶矽晶粒特性，因此具有較好的導通特性以及較低的關閉狀態漏電流。

In this thesis, several effective ways were proposed to improve the electrical performances of polycrystalline silicon thin-film transistors (poly-Si TFTs). First, solid-phase crystallized (SPC) poly-Si TFTs with high-k Pr2O3 gate dielectric were proposed. In addition, applying two kinds of fluorination techniques including fluorine ion implantation and CF4 plasma treatments to the SPC poly-Si Pr2O3 TFTs were deeply investigated. Besides, SPC poly-Si TFTs with two poly-Si grain-size enlargement techniques were demonstrated and characterized. Finally, a simple sidewall spacer technique was developed to fabricate SPC and metal-induced lateral crystallized (MILC) poly-Si TFTs with NW channels. First, high-performance SPC poly-Si TFTs integrated with TiN metal gate and high-k Pr2O3 gate dielectric have been demonstrated. Using the Pr2O3 gate dielectric can obtain thin equivalent-oxide thickness and high gate capacitance density, and then induce much more mobile carriers in the poly-Si channel region. Hence, the grain-boundary trap states in the poly-Si films could be quickly filled up by the large amount of induced carriers to improve the subthreshold swing. The electrical characteristics of the poly-Si Pr2O3 gate dielectric TFTs can be greatly improved compared to those of the traditional poly-Si SiO2 gate dielectric TFTs even without additional hydrogenation treatments or advanced phase crystallization techniques. Then, we have incorporated two kinds of fluorination techniques including fluorine ion implantation and CF4 plasma treatments into the poly-Si Pr2O3 gate dielectric TFTs. Utilizing these fluorination techniques, fluorine atoms can be introduced into the poly-Si films and the Pr2O3 gate dielectric/poly-Si channel interface to passivate the grain-boundary trap states. Hence, the electrical performances and threshold-voltage rolloff properties of the poly-Si Pr2O3 gate dielectric TFTs can be significantly improved by the incorporation of fluorine atoms, in particular, a more obvious enhancement on the decreasing of the off-state leakage currents. Besides, these fluorination techniques also enhance the immunity against hot-carrier stress, due to the formation of strong Si-F bonds in place of weak Si-Si and Si-H bonds. Next, we have developed two kinds of poly-Si grain-size enhancement techniques associating with surface-nucleation SPC scheme including deep Argon ion implantation into the □a-Si/underlying SiO2 interface and novel floating-channel structure. The silicon grain nucleation at the interface is effectively suppressed, and then the nucleation process with fewer nucleation sites will initiate on the a-Si free surface. Fewer silicon grain nucleation results in better poly-Si grain crystallinity with larger grain size and fewer microstructural defects. The electrical characteristics of the poly-Si TFTs are greatly improved by introducing these poly-Si grain-size enhancement techniques. Finally, we demonstrate a simple sidewall spacer technique for forming self-aligned 50-nm line-width nanowire (NW) channels without any advanced lithography process. Poly-Si TFTs with NW channels crystallized by SPC and metal-induced lateral crystallization (MILC) techniques are investigated. The SPC poly-Si NW TFTs have excellent gate controllability over the NW channels due to the three-dimensional (3-D) tri-gate-like structure with the sidewall and corner contribution effects. On the other hand, the MILC poly-Si NW TFTs exhibit better turn-on characteristics and lower off-state leakage currents due to the superior poly-Si grain crystallinity.