適用於雙重視訊標準的可調式動作補償記憶體架構

Abstract

近年來，對於已被先進的數位電視廣播系統採用的 MPEG-2 和 H.264/AVC 視訊標準，其需求是很必要的，動作補償的計算量通常占了整個視訊解碼系統的大多數，這是由於它需要對儲存畫面的記憶體有相當大量的資料傳輸。特別在目前最先進的 H.264/ AVC 視訊標準支援了更高的移動解析度，因而使得所需的記憶體頻寬大量增加。我們提出的擴充性 2x2 光柵式掃描(extended 2x2 raster scanning order)除了可有效地減少所需的記憶體頻寬之外，同時維持和殘餘係數解碼器相同的解碼順序。和傳統的架構相較之下，針對 MPEG-2/ H.264 提出可重新架構的小數點內插器，可省下 20 % 的邏輯閘數量。此外，針對視訊解碼器而提出的 SDRAM 畫面記憶體存取控制器可將頻寬使用率提升至 85 ~90 % 且減少資料存取的延遲達 50 ~90%。在這同時，整個視訊解碼器的資料量處理能力也會提升。我們的視訊解碼器合併了 H.264 Baseline Profile @ 3.2 Level 和 MPEG-2 Simple Profile @ Main Level，而高畫質視訊的即時解碼能力對 H.264 而言可達到 720 HD @ 56 MHz，對 MPEG-2 而言可達到 1080 HD @ 79.4 MHz，而總邏輯閘數量為 491 K，其中包含 23.5 KB 的 on-chip SRAM。

In recent year, MPEG-2 and H.264/AVC video decoding system, which has been adopted by the advanced digital video broadcasting terrestrial/handheld (DVB-T/H) system, is in great demand. The computation time of motion compensation always dominates the entire video decoding system due to the tremendous data transfer with frame memories. Especially in the state-of-the-art video standard, H.264/ AVC, the requisite memory bandwidth is greatly increased because the higher motion resolution requires larger interpolation. The proposed data-reuse technique, extended 2 x 2 raster scanning order, can efficiently reduce the required memory bandwidth when maintaining the same decoding order as that of residual decoding. The proposed reconfigurable interpolator providing fractional interpolation for MPEG-2/H.264 can reduce 20 % gate count compared to traditional design. In addition, the proposed SDRAM frame memory access controller for video decoder increases the bandwidth utilization up to 85~95%, and reduces access latency by 50 ~90% compared to the un-scheduling memory access. In the meanwhile, the throughput of our video decoder is also improved. Our video decoder combined H.264 Baseline Profile @ 3.2 Level and MPEG-2 Simple Profile @ Main Level and the decoding capability of high definition television can reach 720HD at 56 MHz for H.264, 1080HD at 79.4 MHz for MPEG-2 real-time video decoding with total 491K gate count included 23.5 KB on-chip SRAM.