超寬頻無線網路應用之低功率互補金氧半類比數位轉換器設計

Abstract

本篇論文提出利用0.18微米互補金氧半製程實現一應用於低功率極寬頻無線通訊系統的五位元，每秒10億次的快閃式類比數位轉換器。提出一結合串級電阻平均技術和數位錯誤校正技術的高效率架構。對於平均技術和數位校正技術的原理有詳細的分析和討論。藉由結合的技巧，在前級放大器可省85%的功率消耗且減少2N-1個管線式閂鎖的功率。在微分非線性度和積分非線性度的結果分別低於0.3LSB和0.7LSB。信號對雜訊失真比在信號為2.9百萬赫茲時為30.5分貝在475百萬赫茲時為29分貝。整個類比數位轉換器的消耗功率包含前級放大器，比較器，時脈緩衝器和數位錯誤校正電路在1.8伏特的電壓下消耗86毫瓦，使得FOM只有3.9p焦耳。 信號對雜訊失真比在800 百萬赫茲的取樣頻率以及輸入信號為1.07百萬赫茲時的量測結果為29分貝。所量測到的微分非線性度和積分非線性度為 +0.32/-0.22 LSB和 +0.39/-0.24 LSB。計算出的等效位元為4.5位元。

A CMOS 5-bit 1GSamples/s flash analog-to-digital converter (ADC) implemented in 0.18-□m CMOS technology for low-power ultra-wideband (UWB) wireless applications is presented. A power-efficient architecture by combining the cascade resistive averaging and digital error correction technique is proposed. The principle of averaging technique and digital error correction is analyzed and discussed in detail. With the combining techniques, 85% power saving in preamplifiers is achieved and the power of 2N-1 pipeline latches is eliminated. The results show peak differential-nonlinearity (DNL) and integral-nonlinearity (INL) is less than 0.3LSB and 0.7LSB. The signal-to-noise-plus-distortion ratio (SNDR) at 2.9MHz is 30.5dB and the SNDR at 475MHz is 29dB. The total ADC including preamplifiers, comparators, clock buffers and digital error correction circuits consumes 86mW from 1.8V supply, leading to a figure of merit is merely 3.9pJ. The measurement of the SNDR is 29dB under 800MHz sampling rate and 1.07MHz input frequency. The measured DNL and INL are +0.32/-0.22 LSB and +0.39/-0.24 LSB. The effective number of bits (ENOB) is calculated equal to 4.5 bits.