通訊系統晶片設計之模擬驗證平台

Abstract

在這篇論文中，我們介紹了一個結合了硬體模擬和通訊系統模擬的模擬驗證平台。在系統晶片設計流程中，硬體模擬是一個非常重要的步驟。而通訊系統模擬則是通訊系統研究中不可或缺的工作。這篇論文提出了一個結合了多項功能的平台，包含了硬體模擬，通訊系統模擬，以及軟體發展驗證。對於通訊元件的設計實現，這個將可平台提供一個方便的環境。在論文中，將會對這個平台的各個重要元件的設計理念及工作方法做詳細的描述。

This thesis introduces a development and verification platform that combines hardware modeling and communication system simulation. The hardware modeling is an important technology in SoC design process, and system simulation is an essential process in communication system designs. This proposed platform enables the use of a single platform for multiple-purpose designs for communication system designs, including system simulation, software development and hardware modeling. The platform is especially useful for the designs of communication components whose behaviors are highly coupled with transmission medium and other parallel components. The basic platform components and design strategies are also described in this thesis.