Low-Threshold-Voltage TaN/LaTiO n-MOSFETs With Small EOT

doi:10.1109/LED.2009.2027723

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lin, S. H.	en_US
dc.contributor.author	Cheng, C. H.	en_US
dc.contributor.author	Chen, W. B.	en_US
dc.contributor.author	Yeh, F. S.	en_US
dc.contributor.author	Chin, Albert	en_US
dc.date.accessioned	2014-12-08T15:08:49Z	-
dc.date.available	2014-12-08T15:08:49Z	-
dc.date.issued	2009-09-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/LED.2009.2027723	en_US
dc.identifier.uri	http://hdl.handle.net/11536/6730	-
dc.description.abstract	In this letter, we report a low threshold voltage (VI) of 0.12 V in self-aligned gate-first TaN/LaTiO n-MOSFETs, at an equivalent oxide thickness of only 0.63 run. This was achieved by using Ni-induced solid-phase diffusion of SiO(2)-covered Ni/Sb that reduced the high-kappa dielectric interfacial reactions.	en_US
dc.language.iso	en_US	en_US
dc.subject	LaTiO	en_US
dc.subject	low V(t)	en_US
dc.subject	solid-phase diffusion (SPD)	en_US
dc.title	Low-Threshold-Voltage TaN/LaTiO n-MOSFETs With Small EOT	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/LED.2009.2027723	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	30	en_US
dc.citation.issue	9	en_US
dc.citation.spage	999	en_US
dc.citation.epage	1001	en_US
dc.contributor.department	機械工程學系	zh_TW
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Mechanical Engineering	en_US
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000269443000036	-
dc.citation.woscount	8	-
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