可規畫式系統晶片架構之研究

Abstract

時下資訊家電及通訊產品快速的發展，系統晶片上的設計已成為這爆炸性成長的關鍵因素。然而目前最先進的系統晶片設計就是利用智財為底的方式來設計，這種設計方式給予設計者很多的挑戰，特別是在演算法的轉換及智財元件的整合。為了簡輕設計系統晶片的困難，在這篇論文當中提出一個新的資料流架構來整合智財元件。這架構利用派翠網路產生運算單元的動態排程，以達到所需數位訊號處理演算的操作，進行有效率的資料流計算。這個以派翠網路以底所發展出來的排程器可以處理運算時間和內部處理器之間的通訊時間不定的系統，被提出的系統晶片架構是針對數位訊號處理應用而可重新規畫的系統。

Nowadays, the industry of information appliances and communication products is growing rapidly. System-On-Chip(SOC) design has been becoming the key to enable the explosive growth. However, the state-of-the-art SOC design is rather IP-based and provides several challenges to designers, especially in the transformation of algorithms and the integration of IP cores. To alleviate the difficulty of SOC design this thesis proposes a novel dataflow architecture for the integration of IP cores. The proposed architecture employs the Petri Nets to dynamically schedule the operations of DSP algorithms onto processing elements and, hence, efficiently performs dataflow computing. As a result, the Petri-Net-based scheduler is insensitive to the timing of computation and interprocessor communication, and the proposed SOC architecture is reconfigurable for DSP applications.