先進大型積體電路整合之製程設計與元件特性

Abstract

本論文主要討論混波與射頻單一晶片之製程整合與元件特性研究。矽金氧半電晶體迅速的技術演化使得元件速度持蓄地提高和成本快速的降低。除關於低頻性能的增加以外，CMOS 技術的提昇已經顯著改進元件的高頻特性。最顯著的改進是更高的截止頻率 (ft), 更高的最大振蕩頻率 (fmax), 以及更好的相稱性 (matching)。這使得 CMOS 成為混波與射頻系統單晶片(SoC)的首要選擇。 單一晶片無線電設計需要整合用於基頻信號處理的高性能類比元件，用於低雜訊放大器和混波器的高性能射頻電晶體和被動元件，和用於電源管理的高壓元件。 在這篇論文裡，我們討論整合 金屬-絕緣-金屬(MiM) 電容器於標準 CMOS邏輯製程後段(BEOL)銅製程的製程考慮。 在銅被因為更好的速度考慮引入 CMOS 製程技術之前，鋁銅(AlCu) 被作為 MiM 電極架構的電容器被廣泛地使用。因為鋁銅(AlCu) 本身也被作為 CMOS 邏輯製程後段的互聯導線(Interconnect) 使用。如果使用銅作為電容器的下電極時會遭遇到不同的問題。我們比較了使用不同材料作為電容下電極板時的製程和性能以及示範怎樣把 MiM 電容器整合進入銅製程。 設計一個單晶片發報機最難的部分在於需要將功率放大器整合起來。這由於 CMOS 電晶體的低源極崩潰電壓, 使得 CMOS 在功率放大器的使用受到了限制。 這個高電壓操作的限制顯著降低了 CMOS 元件的最大的輸出功率和功率效率。 為解決這一個問題, 我們設計了新的非對稱性 LDD 的金氧半電晶體以增加源極崩潰電壓。 這一個新的元件在峰值功率增益(PAE) 點時輸出功率被改進了38%。 同時在 10 dbm 輸出功率及 2.4 GHz 操作頻率時, 功率增益亦改善了16%。這個新電晶體的顯著性能改善使得 RF-CMOS 系統單晶片往前又跨出了一步。 本文將討論與單晶片整合時需要考量到的問題,包含了射頻特性最佳化的方法以及雜訊模型, MiM電容器整合入銅的後段製程時的製程設計, 和一個用於提昇射頻功率的新的非對稱 CMOS 元件。

This thesis proposes process integration and device characterization of metal-insulator-metal capacitors and asymmetric-LDD MOS transistor for SoC design. The rapid technology evolution of Si MOSFET is driven by higher device speed and cost reduction. Besides the benefit on digital performance, the scaling of CMOS technology has significantly improved the RF performance of MOS devices. The most significant improvement along with CMOS technology scaling is the higher cut-off frequency (ft), higher maximum oscillation frequency (fmax), and better matching. This has made CMOS the prime choice for RF system-on-chip (SoC). The single chip transceiver design requires integration of high-performance analog components for base-band signal processing, high-performance RF transistors and passive components for low noise amplifiers and mixers, and high voltage components for power management. In this dissertation, we discussed the process consideration of integrating the high-quality Metal-Insulator-Metal (MiM) capacitors into the Cu Backend-of-Line (Cu BEOL) of standard CMOS logic process. AlCu was widely used as the electro-plates of MiM structures before copper was introduced into the process technology for better speed consideration. This is because AlCu is also used as the interconnection of the BEOL logic process. In the Cu era, there are different issues with the Cu electro-plates if used as a part of MiM capacitors. We compared the process and performance among different materials of MiM electro-plates and demonstrated how to integrate the MiM process into the Cu BEOL. A difficult part to design a single-chip transceiver requires the integration of the power amplifier. However, the low drain breakdown voltage of CMOS transistors limits the use of CMOS in power amplifiers. This limitation for high voltage operation significantly reduces the maximum output power and efficiency of CMOS devices. We had designed a new asymmetric-LDD MOSFET to increase the drain breakdown voltage. The output power is improved by 38% at peak power-added efficiency. The significant improvements of RF power performance by this new MOS transistor make the CMOS SoC design a step further. In conclusion, the integration of RF-SoC design including RF performance optimization method, RF noise modeling, the process consideration of integrating the MiM capacitors into Cu BEOL, and a new asymmetric CMOS device were discussed in this dissertation.