具預先增強與準位自動校正之驅動電路

Abstract

由於製程技術的進步，CMOS積體電路的操作頻率及電路複雜度也隨著增加。使得晶片內部的邏輯閘以及連結外部的輸入/輸出介面之間的頻寬差距到達嚴重的比例。因此，連接晶片之間的傳輸通道時常限制了系統的效能，這些系統包括網路的切換器、路由器、處理器和記憶體之間的介面及多處理器的傳輸通道。 在此論文中，我們將簡單的介紹高速序列傳收機。我們提出一個可增強高頻區段訊號的預先增強電路，使資料在接收端能在操作頻率下維持一定值。接著，我們再加上自我校正功能，可以對輸出電壓準位做自動的調整，以防止製程漂移或溫度變化而造成輸出準位的誤差。再者，我們可以決定近端電阻與驅動電路的等效阻值使其輸出阻抗接近50歐姆，進而減少反射所造成的影響，實現此電路技術及設計概念也將再論文中說明。 論文中，我們將實現一個符合低電壓差動訊號標準3.125 Gbps的傳送器。此傳送器是使用台積電0.18μm CMOS製程製作且在1.8V的供應電壓下其功率消耗為50毫瓦。

Due to the scale-down of the process technologies, the operating frequency and circuit complexity of CMOS VLSI increase significantly. The growing gap between on-chip and off-chip I/O bandwidth is reaching the critical proportions. Therefore, the interconnections between chips often limit the performance of a system in applications such as network switches, routers, processor-memory interfaces, and multi-processor interconnects. For this reason, to integrate high speed serial links on chips can reduce the pin/wire count and power budget of a system significantly. In this thesis, we will introduce a high-speed serial link. We will propose the pre-emphasis circuit that can enlarge the high frequency components, so the overall frequency response at the receiving end is uniform across the operation frequency. Then we add the self-calibration function to our driver so that it can calibrate itself automatically to deal with process or temperature variation. In order to reduce the reflection effect, we can determent the termination resistor value of near end and the equivalent resistors of the driver to make these resistors be equal to 50 in steady state. The circuit design will be described in detail. In this thesis, a 3.125 Gbps transmitter has been designed. It is compatible with the LVDS standard. In a TSMC 0.18-μm 1P6M CMOS technology, the transmitter circuit consumes 50mW on a 1.8V power supply.