極高速快閃式類比數位轉換器

Abstract

由於製程技術的進步，CMOS積體電路的操作頻率及電路複雜度也隨著增加。介於類比與數位之間的介面需要極高速的操作速度，約是每秒幾百萬次取樣到每秒幾億次取樣不等。這些高傳輸率的系統，包含DVD讀取通道、多準位接收器、通道等畫器、時脈抖動量測系統或乙太網路都需要類比數位轉換器。 在這篇論文中包含了兩個主題。首先，我們將焦點放在高速類比數位轉換器的電路設計方法，因此我們提出一個在一般能操作於每秒31.25億次取樣，最高可操作於每秒40億次取樣的4位元快閃式類比數位轉換器，這個4位元快閃式類比數位轉換器在輸入頻率高達每秒15.5億時用每秒31.25億次取樣的情況下能有超過3.1的有效位元，而在輸入頻率高達每秒20億時用每秒40億次取樣的情況下能有超過2.3的有效位元。它的最大差分非線性誤差與積分非線性誤差分別小於0.45與0.6最小位元。這個類比數位轉換器操作於1.8伏特的電源供應且每秒40億次取樣時消耗180毫瓦，這晶片使用TSMC 0.18-um 1P6M CMOS實做時佔了0.36- 的面積。 接著，我們根據4位元快閃式類比數位轉換器的電路，我們提出了兩個方法使得4位元的精準度提高到5位元的精準度。這兩個方法分別是主動式平均技巧與主動式內插技巧，使用主動式平均技巧可以得到較高的精準度，但使用主動式內插技巧卻可以節省較多的功率消耗。這個使用了主動式平均技巧的5位元快閃式類比數位轉換器在輸入頻率高達每秒15.5億時用每秒31.25億次取樣的情況下能有超過3.8的有效位元，而在輸入頻率高達每秒20億時用每秒40億次取樣的情況下能有超過3的有效位元。它的最大差分非線性誤差與積分非線性誤差分別小於0.35與0.8最小位元。這個類比數位轉換器操作於1.8伏特的電源供應且每秒4億次取樣時消耗270毫瓦。這個使用了主動式內插技巧的5位元快閃式類比數位轉換器在輸入頻率高達每秒15.5億時用每秒31.25億次取樣的情況下能有超過3.6的有效位元，而在輸入頻率高達每秒20億時用每秒40億次取樣的情況下能有超過2.9的有效位元。它的最大差分非線性誤差與積分非線性誤差分別小於0.5與0.9最小位元。這個類比數位轉換器操作於1.8伏特的電源供應且每秒4億次取樣時消耗243毫瓦。

Due to the advance process technologies, the operating frequency and circuit complexity of integrated circuit increase. The interfaces between the analog and the digital parts are required to operate at ultra high speed (over giga samples per second). The high-bit-rate applications include DVD read channel, multi level receiver, channel equalizer, jitter measurement system, and Ethernet need Analog-to-Digital Converters. There are two major topics in this thesis. First, we focus on the high speed ADC circuit design. Thus, we propose a 4-bit flash ADC typically operates at 3.125GSps and maximally at 4GSps. This 4-bit ADC achieves better than 3.1 effective bits for input frequencies up to 1.55GHz at 3.125GSps, and 2.3 effective bits for 2GHz input at 4GSps. The peak DNL and INL are less than 0.45 LSB and 0.6 LSB, respectively. This ADC consumes 180mW from 1.8V power supply at 4GSps. The chip occupies 0.36- active area, implemented in TSMC 0.18-um 1P6M CMOS. Second, based on the circuits presented in the 4-bit flash ADC, and we propose two methods to improve the 4-bit accuracy to 5-bit accuracy. The methods are active averaging and active interpolation techniques. Using averaging technique can improve accuracy white using interpolation technique can reduce power consumption. The 5-bit flash ADC with averaging technique achieves better than 3.8 effective bits for input frequencies up to 1.55GHz at 3.125GSps, and 3 effective bits for 2GHz input at 4GSps. The peak DNL and INL are less than 0.35 LSB and 0.8 LSB, respectively. This ADC consumes 270mW from 1.8V power supply at 4GSps. The 5-bit flash ADC with interpolation technique achieves better than 3.6 effective bits for input frequencies up to 1.55GHz at 3.125GSps, and 2.9 effective bits for 2GHz input at 4GSps. The peak DNL and INL are less than 0.5 LSB and 0.9 LSB, respectively. This ADC consumes 243mW from 1.8V power supply at 4GSps.