利用模擬器建構之 AMBA AHB 匯流排介面驗證系統

Abstract

從六零年代起, IC工業依照著 Moore’s law (每十八個月 IC 的容量會增加一倍)快速的發展. 如此一來, IC 設計的複雜度增加也使得設計驗證更加的困難. 另一方面, 設計者也面臨產品的研發週time-to-market (TTM) 和設計驗證過程完整度之間重大的取捨. 其次, 一種新的設計方法, 系統單晶片 (SOC), 它的目的是在追求產品設計成本的降低和縮短產品研發週期. 所有的矽智財元件將被整合在一顆單一晶片中,但是隨之而來的問題是使得設計驗證將會更形複雜. 藉由傳統的設計驗證方法, 設計者必須花費龐大的時間與努力來找到錯誤所在. 我們改進既有產生測試樣本的方法建立一套更加方便的設計驗證環境來驗證AMBA AHB 設計. 利用一個用 C 程式語言所建立的模擬器, 我們在驗證我們所設計的 AMBA AHB 時, 花費了更少的努力和時間卻得到了更令人滿意的結果. 此外,其他的 AMBA AHB 設計者也可以利用我們的驗證系統及方法進行驗證, 這個驗證系統並不被限制只能夠使用在驗證我們的 RTL 設計上.

Since the 60s, the IC industry has made significant progress following Moore’s law: “the volume of the IC doubles per 18 months”. Moreover, System-on-chip (SOC) solution, a new design methodology, addresses cost-efficiency. That is, using this methodology, all intellectual property (IP) is integrated into a single system. As a result of the increasing complexity of the RTL design, verifications become more and more difficult. Due to the great increase in gates/pins ratio, all designers are facing a big trade-off between the verification process and time-to-market (TTM). With the traditional ways of verification methodologies, designers need to spend enormous time on finding errors. We improved the conventional test pattern generating method into a more convenient environment to verify the AMBA RTL designs. With the simulator of AMBA AHB written in C language, less effort and time were spent in our design flow but more satisfying result was achieved when we verified our AMBA AHB design. In addition, with the system and methodology we provide, all AMBA AHB RTL designers can also conduct their verifications. Our verification system is not usable only for our AMBA AHB design.