標題: 採用Σ-Δ調變之全橋功率放大器
A Full-Bridge Class-D Amplifier Using Sigma Delta Modulation
作者: 陳鏗元
Kang-Yuan , Chen
胡竹生
Jwu-Sheng, Hu
電控工程研究所
關鍵字: Σ-Δ;D類放大器;sigma delta;class D
公開日期: 2004
摘要: 本論文以Σ-Δ為調變基礎設計並實現一數位功率放大器,以切換式訊號為輸入之數位功率放大器相較於類比A/B類,擁有體積小、功率效益較高的優點,而其重點在於可將任意訊號調變為單位元表示之前級訊號調變器,相較於常見的PWM調變法,Σ-Δ調變器沒有倍頻雜訊,其較低的切換次數使系統減少切換損失。本論文將證明與分析高階Σ-Δ系統於單位元與1.5位元運算之穩定特性,由結果可以知道1.5位元運算於雜訊抑制的能力,以及切換次數之減低皆優於單位元運算。數位Σ-Δ調變器將實現於FPGA,並配合後級之全橋功率放大器,作雙聲道之音頻訊號的放大與撥放。
This thesis proposes a design of full-digital class-D amplifier using sigma-delta modulation. The class-D amplifier operating the MOSFET (or IGBT) in saturation mode has the advantages of smaller size and higher power efficiency over traditional class-A/B ones. The underlying principle of generating the switching command is to convert the input signal into an oversampled binary signal. Compared with PWM modulation, sigma-delta modulation produces less distortion, noise and number of switching. The design and stability analysis of digital sigma-delta modulation are studied in this thesis using both 1- and 1.5-bit quantization schemes. The results show that the 1.5-bit scheme further improves the noise shaping performance and switching number reduction. The digital sigma-delta modulator is implemented on an FPGA and a full-bridge power stage is constructed to verify the design method. The resulting experimental platform is able to achieve a stereo amplifier with 22.05KHZ audio bandwidth.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009212559
http://hdl.handle.net/11536/68557
Appears in Collections:Thesis


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