藉由非理想特性與功率分析達到三角積分類比數位轉換器之最佳化設計

Abstract

由於傳統的積分三角類比數位轉換器設計過程需花費大量的時間和需要經過許多的錯誤嘗試。因此，在本篇論文中，我們提出一個針對積分三角類比數位轉換器的最佳化設計演算法。 首先我們必須透過了解電路上的不完美特性， 來建立積分三角電路的非理想特性模型，而為了估測其功率消耗，我們亦嘗試建立功率消耗模型。我們發現在積分三角調變器的電路中，各項設計參數如超取樣比、量化位元數…等的變化均有可能造成雜訊功率的改變，甚至造成整體功率消耗的變化。而不同設計參數的組合，亦可能會造成在系統效能上相當大的差異，所以我們在設計積分三角調變器時，需要一組最佳化的設計參數。我們所提出的最佳化演算法可以找出在特定系統規格下，能達到最大權重函數的一組設計參數，通常這便是所需的最佳化參數。這套演算法是由Mathematica這套數值軟體建構而成。最後我們將針對兩篇已發表的設計結果來做驗證的工作。

An optimization algorithm for the design of sigma delta ADCs is proposed. Conventional sigma delta ADCs design approach is a time consuming process and needs much trial and error. Through a systematic study of circuits’ imperfections, circuit nonidealitiy models are derived in output noise power forms. Power model is also presented in order to estimate the relative power consumption. Through analyzing the models, it is clear that variation of a design parameter can potentially affect several noises and errors in different ways, and may change system power rate. This complexity is qualitatively summarized into a table. The completeness of models allows us to propose an optimization algorithm to search globally for a combination of design parameters which meet the design specifications while minimizing power consumption. Our optimization algorithm is tested against two published design results. Some design discrepancies are observed, and they are analyzed and discussed. Parameter sensitivity issues are also visited.