深次微米元件之低頻雜訊分析

Abstract

在類比電路應用中，降低雜訊為一項重要議題，也限制了訊號的精確度和可測性；而隨著射頻積體電路的需求日益增長，使深次微米元件之低頻雜訊研究更形迫切，主要乃因低頻雜訊將倍頻而影響非線性電路及元件之高頻相位雜訊。此外，雜訊受製程技術影響深遠，故可用以了解元件特性並預測其衰退機制。 本篇即以 Unified Noise Model 為基礎，探究元件低頻雜訊的來源，討論各項相關議題。首先，研究元件微縮對雜訊之影響，了解元件雜訊變異及載子分佈N(y)、通道長度L與雜訊之關係，此外，將介紹利用低頻雜訊量測萃取元件spacer下之缺陷密度的方法。其次，探討不同退化機制對雜訊之變化情形，確立不規則的臨界電壓VT將導致雜訊增加。最後，略述深次微米元件中一些特殊先進製程步驟對雜訊之效應，並介紹可降低雜訊之製程。

Interest in low-frequency noise behavior of deep-submicron Si MOSFETs is first of all drawn by analog applications, where noise minimization is a key issue in circuit sensitivity and detection. Nowadays, low frequency noise receives growing attention from RF community as well. The reason is that low-frequency noise potentially has an impact on the phase noise of nonlinear circuits and devices in the GHz regime. The third motivation for this study is that noise is a sensitive technology parameter, which can be used as a predictive or a diagnostic tool for the durability and reliability of a device. The main theme of this work will focus on the origin of noise in MOSFETs. Based on the unified flicker noise model, several issues will be addressed. Firstly, the impact of device scaling on flicker noise will be investigated. Carrier distribution and channel length dependence of noise behavior will be discussed. Furthermore, we will introduce a 1/f noise technique to extract oxide trap density in the spacer region of a MOSFET. Secondly, attention will be paid to the correlation between different stress modes with flicker noise degradation. It was observed that the non-uniform distribution of threshold voltage along the channel has a large effect on noise degradation. Finally, the dependence of noise on device processing steps will be studied. Guidelines for low-noise processing will be recommended.