一個900M Hz低功率之鎖相迴路設計

Abstract

探討如何降低雜訊對PLL的干擾以減少Jitter為本論文的目標。本論文以一個PLL的實際電路模擬來分析造成Jitter的原因及可能的解決方法，不過並沒有提出改善的實際電路結構。我的分析集中在環形振盪器(Ring Oscillator)中產生延遲時間的電路(buffer或delay cell)。結果得到(1)buffer的負載若其 特性曲線能越接近理想的直線，亦即純電阻，對電源電壓雜訊的免疫力越高，否則若能限制buffer的輸出振幅小一點也可提升其雜訊免疫力。(2)證實buffer replica feedback技術對於抑制靜態電源電壓雜訊並沒有用。 這個PLL電路的操作頻率在900m Hz，使用0.35uM TSMC 1P4M製程，外部訊號參考頻率為56.25M Hz，VCO的輸出頻率範圍為1080M Hz~720M Hz，亦即900M Hz 20%，做到post-simulation。

The purpose of this thesis is to reduce noises and non-ideal effects on the PLL circuit operation for jitter suppression. We used a real PLL circuit simulation to analyze the reason that causes the jitter and find out possible solutions. Our study focused on the analysis of the circuit that generates delay time in a ring oscillator. We found that better noise rejection could be achieved through making the I-V characteristic of the load resistance of the buffer as linear as possible or limiting the amplitude of the VCO as small as possible. We also proved that the buffer replica feedback technique has little effect on the suppression of the static power supply noise. The designed PLL circuit is not implemented, but post simulation. The circuit can operate at 900M Hz, using 0.35□m TSMC 1P4M process. Its reference clock is 56.25M Hz, and the VCO output-frequency is between 1080M~720M Hz, i.e. 900M Hz ± 20%.