針對迴旋編碼的維特比解碼機中倖存路徑器之改良

Abstract

在本論文中，我提出三種新的倖存路徑記錄器之設計來分別改良三種傳統倖存記錄器實現方法的缺失。對路徑回溯法(Traceback Management)而言，它原本就具備低功率消耗及較小的電路面積，但最為詬病的是其過程需要長時間的延遲(Decoding latency)。針對路徑回溯法，我提出跳階路徑回溯法(Stage-Hopping TBM).改良後的解碼效率隨著強制長度(Constraint Legnth)的增加可以逼近暫存器交換法(Register Exchange)的解碼效率。除此之外，改良後的跳階回溯法所用來記錄路徑的記憶體量只需原來路徑回溯法的45%。因此跳接路徑回溯法可同時改善維特比解碼機的解碼效率以及硬體的複雜度。 對於暫存器交換法而言，儘管它有最短的解碼延遲，它的功率消耗以及電路面積卻是三種傳統方法中需要最大的，原因在於暫存交換法所需要極大量的暫存器與多工器(Multiplexer)將倖存路徑儲存於正確的位置中。因此，我提出了簡易暫存器交換法(Facilitated REA)，主要目的就是要減少實現暫存器交換法所需的硬體，而改良後的方法可以發現，原本多個多工器可以被單一個取代而不影響解碼的效果。 對於混合法(Hybrid Method)而言，其原本被提出的目的就是要藉由結合路徑回溯法與暫存器交換法的優點來中和兩者的缺點，因此可以明顯的發現，前述提出的改良方法皆可同時應用在混合法中，以求進一步的改善實現混合法所需的硬體複雜度。 在所提出的三個新方法中，用來查詢出路徑對應輸入信號為何的解碼單位(Decision Unit)都是不被需要的，因此些許的硬體和解碼延遲都可以再被減少。總結而言，藉由C語言的模擬可以發現，新提出的倖存路徑記錄器設計並不會因為改良硬體需求與解碼效率就犧牲解碼能力。藉由圖形表示法(Graphic representation)，三種改良方法的解碼效率和硬體需求都可以被詳細檢視與比較，藉此可看出每種新提出的改良設計所能獲得的好處。

In the thesis, three new approaches are proposed to improve the drawbacks of three corresponding methods that are used conventionally in the realization of survivor memory unit (SMU) in Viterbi Algorithm (VA) as convolution decoders. For trace-back management (TBM) method, it has owned the virtues as low power consumption and small circuit area, but suffers long decoding latency. Corresponding to TBM, Stage-Hopping TBM (SH-TBM) is developed. The decoding efficiency can be raised approaching to the performance of register exchange algorithm (REA) as constraint length increases. On the other hand, length of the required memory could be reduced down to about 45% of the length originally required in TBM at most. REA obtains shortest decoding latency, however, with large power consumption and circuit area caused by the required numbers of registers and multiplexers. To ameliorate the disadvantage, Facilitated REA (FREA) is proposed with a concept that multiple of multiplexers can be replaced by a single one without affecting the decoding performance. As for Hybrid method, it is originally designed to balance the trade-off between decoding efficiency and the required quantity of hardware by combining TBM and REA. Therefore, Improved Hybrid method (IHY) naturally inherits the technique used in FREA and SH-TBM. As expected, fewer multiplexers, in some cases only one column of multiplexers, will be needed and traceback operation could be realized faster. Of all three newly proposed methods, decoding unit (DU) is eliminated. Hence, a slight more increase in speed and decrease in hardware could be acquired. In summary, the experimental result simulated by C program shows that proposed methods do not deteriorate the decoding performance anyhow. By graphical methods, analyses and comparisons are made to demonstrate the improvements in hardware reduction and the acceleration in decoding efficiency.