邏輯合成低耗電之非同步電路

Abstract

在一大型的電路中，根據一些論文可知，同步時脈在整個電路中佔了很大的面積，同時也佔了整體耗電量約30%，所以說減低耗電量成為了一個重要的話題。基於這個理由，所以我們將採用一種新的電路設計方式﹕非同步電路設計，然後再發展出一有效的方法來邏輯合成低耗電電路。 在這篇論文中，我們使用了一個新的估算耗電量方法，來邏輯合成所給的邏輯方程式，以達到低耗電的目標。這個估算耗電量之方法的名字叫：FR-vector，它可以對一所給的組合邏輯電路和其所輸入之訊號，此組合邏輯電路我們必須先將其根據技術來做邏輯分解，然後可以準確地估算出該組合邏輯電路內部邏輯閘所輸出之訊號的變化次數，也就是耗電量。此方法可以快速地估算出訊號變化次數，它可以紀錄訊號變化的發生，同時在其計算中也可以表現出訊號變化的繁殖和消除，另外對於突波之產生、繁殖和消除也可以表現出來。 利用這個估算耗電量之方法，對於所給于的邏輯方程式，我們可以找出用來做無危障邏輯合成所需要的動態無危障低耗電之素蘊涵項，然後再將這些我們找的動態無危障低耗電之素蘊涵項送進去極小化涵蓋問題中，來找出可以包含該邏輯方程式的省電非同步電路。 我們使用了一些有名的非同步之標準檢查電路來對我們的方法作試驗。從實驗的結果可以看出來，跟一般對面積作邏輯最佳化合成的方式比較起來，我們產生的非同步電路大約可以省6.4%的耗電，其中最好的結果可以省19%的耗電。

In a large circuit design, it is reported that the clock needs considerable portion in area and power consumption, namely 30% power consumption of the circuit. Therefore, improving the power efficiency is deserved to be heavily concerned. In our research, we will follow a new circuit design style, asynchronous system, and then propose an efficient method to decrease the power consumption in a chip. In this paper, in order to reduce power consumption in asynchronous circuits, we use a new power estimating method to do logic synthesis for a given function based on a burst-mode machine. This new power estimating method is called: FR-vector. For a combinational circuit, we give a set of input signals and decompose this combinational circuit based on the technology. Then, this new power estimating method can accurately estimate the number of switching activities of gates inside the combinational circuit. It is also able to model the propagation and the elimination of switching activities. For glitches, it not only can model the propagation and the elimination, but also can model the generation of glitches. By using this power estimating method and based on the two-level hazard-free synthesis, we generate a new set of dynamic hazard-free power prime implicants (dhf-PPIs) for a given function. Then, this set of dhf-PPIs is used to feed into minimum covering problem and generate the low power asynchronous circuit. In the experiments, we use our low power synthesis method to synthesize some famous benchmarks of asynchronous circuits. Comparing to the general synthesis for area optimal, we can find that the power consumption is reduced averagely targeting to 6.4%. For the best case, the reduced power consumption is even more targeting to 19%. Therefore, we can say that our method is effective for reducing power consumption of logic synthesis.