完整後設資料紀錄
DC 欄位語言
dc.contributor.author王仲益en_US
dc.contributor.authorChung Wang Ien_US
dc.contributor.author溫瓌岸en_US
dc.contributor.authorKuei-Ann Wenen_US
dc.date.accessioned2014-12-12T02:30:48Z-
dc.date.available2014-12-12T02:30:48Z-
dc.date.issued2002en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT910428156en_US
dc.identifier.urihttp://hdl.handle.net/11536/70486-
dc.description.abstract本篇論文說明一個適用於IEEE802.11a之5120MHz至5440MHz CMOS四相位頻率合成器,包含壓控震盪器,可程式除頻器,相位比較器,電流幫浦以及迴路濾波器。從電路模擬結果中,可得中心震盪頻率以20MHz為參考頻率,震盪範圍在5120MHz至5440MHz,訊號大小約為-1dBm且相位雜訊在100kHz時為-103dBc/Hz,載波切換時間為25usec,寄生載波衰減為68dB且總能量消耗為100mW。在量測結果方面,載波頻率範圍在4.133GHz至4.485GHz且相位雜訊在100kHz時為-68dBc/Hz。本頻率合成器是採用UMC 0.18um CMOS 1P6M製程並操作在1.8V的直流電壓。zh_TW
dc.description.abstractA quadrate 5GHz frequency synthesizer used for 802.11a standards will be proposed, including quadrate VCO, programmable frequency divider, phase detector, charge pump and loop filter. For the simulation results, the carrier frequencies are from 5120MHz to 5440MHz with spacing 20MHz, output power is -1dBm and phase noise is -103dBc/Hz at offset frequency 100kHz, the lock time is 25us, the spurious attenuation is about 68dB and the power consumption is 100mW. For measurement data, the frequency range is form 4.133GHz to 4.485GHz with phase noise -68dBc/Hz at offset frequency 100kHz. This frequency synthesizer was realized in UMC 0.18um CMOS one-poly six-metal (1P6M) process and run off of a 1.8V supply.en_US
dc.language.isoen_USen_US
dc.subject頻率合成器zh_TW
dc.subjectRFen_US
dc.subjectCMOSen_US
dc.subject5GHzen_US
dc.subjectsynthesizeren_US
dc.titleIEEE 802.11a CMOS 頻率合成器設計zh_TW
dc.titleCMOS Frequency Synthesizer Design for IEEE 802.11aen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
顯示於類別:畢業論文