完整後設資料紀錄
DC 欄位語言
dc.contributor.author李芊瑢en_US
dc.contributor.authorLi, Chien-Jungen_US
dc.contributor.author蘇朝琴en_US
dc.contributor.authorSu, Chau-Chinen_US
dc.date.accessioned2014-12-12T02:32:17Z-
dc.date.available2014-12-12T02:32:17Z-
dc.date.issued2012en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079812631en_US
dc.identifier.urihttp://hdl.handle.net/11536/71384-
dc.description.abstract本篇論文提出一個可操作於0.5伏特的監測系統,不但能偵測並數量化被傳輸資料的抖動值,且能還原受抖動影響的資料。此系統包含三大部分:驗證用的數位電路、自我動態調節電壓系統、鎖相迴路。被驗證的電路做為傳輸資料使用,其操作電壓被自我動態調節電壓系統最佳化,以期用最低的壓值使資料所受的抖動影響符合系統規格要求。自我動態調整電壓系統又可分成動態調整電壓和時脈與資料回復兩個迴路。前者用來最佳化被監測電路的操作電壓,後者則用來回復受時脈抖動影響的被傳輸資料。自鎖相迴路提供多重相位來達到上述所提的兩迴路功能。 此論文使用TSMC MSG 90nm CMOS製程實現設計。當抖動要求為4/16UI時,自我動態調節電壓系統操作在40MHz和電壓0.5伏特時,功率消耗73.5W,數位電路傳送的資料其抖動值為5.61ns,而被回復的資料抖動值為1.94ns。鎖相迴路操作在40MHz電壓0.5伏特時,所耗的功率消耗為155W,且環形振盪器的輸出峰對峰值抖動為186.87ps。數位電路可操作的電壓範圍在0.24到0.42伏特之間。當數位電路操作在0.34伏特且抖動要求在4/16UI時,功耗是操作在0.5伏特的55.62%。此外,此自我動態調節電壓系統節省數位電路功耗的效率最低31.48%、最高74.97%。zh_TW
dc.description.abstractThe proposed 0.5-V monitoring system detects and quantifies the data jitter. In the meantime, it recovers data as well. The digital circuit transmits the NRZ data, and its supply voltage is scaled by this monitoring system. Consequently, data jitter can meet the systematic specification with minimized voltage. The proposed system can be divided into three parts: the digital circuit (DUT), the self-tuning dynamic voltage scaling system (STDVS), and the phase-locked loop (PLL). The DUT in this system is used to transmit NRZ data. The STDVS system consists of two connected loop, DVS and CDR loop. One is to optimize the supply voltage of the DUT circuit, and the other is to recover the NRZ data transmitted by the DUT circuit from jitter, respectively. The PLL generates multi-phases to achieve the two mentioned function of the STDVS system. The chip is fabricated in TSMC MSG 90nm CMOS technology. The total silicon area is 1mm2, including buffers and PADs. With jitter requirement of 4/16UI, the 0.5-V STDVS system consumes 73.5W at 40MHz. The data jitter of the DUT circuit is 5.61ns and the recovered data jitter of the CDR is 1.94ns. The power consumption of the 0.5-V PLL is 155W, and the VCO’s peak-to-peak jitter is 186.87ps. The DUT circuit can be operated within the voltage range from 0.24V to 0.42V. Compare to 0.5V, the power consumption of the DUT operated at 0.34V is reduced to 55.62% with jitter requirement of 4/16UI. This STDTVS scheme results in energy savings efficiency from 31.48% to 74.97%.en_US
dc.language.isoen_USen_US
dc.subject抖動zh_TW
dc.subject鎖相迴路zh_TW
dc.subject動態電壓調節機制zh_TW
dc.subject時脈與資料回復zh_TW
dc.subject眼圖zh_TW
dc.subjectjitteren_US
dc.subjectphase-locked loopen_US
dc.subjectDVSen_US
dc.subjectclock and data recovery,en_US
dc.subjecteye-diagramen_US
dc.title一個可操作於0.5伏特具時脈抖動偵測並可自我動態調整操作電壓之監測系統zh_TW
dc.titleA 0.5-V Self-Tuning Dynamic Voltage Scaling System with Jitter-Detected Mechanismen_US
dc.typeThesisen_US
dc.contributor.department電機工程學系zh_TW
顯示於類別:畢業論文