Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness

doi:10.1109/LED.2009.2018493

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	Lin, Horng-Chih	en_US
dc.contributor.author	Chen, Wei-Chen	en_US
dc.contributor.author	Lin, Chuan-Ding	en_US
dc.contributor.author	Huang, Tiao-Yuan	en_US
dc.date.accessioned	2014-12-08T15:09:22Z	-
dc.date.available	2014-12-08T15:09:22Z	-
dc.date.issued	2009-06-01	en_US
dc.identifier.issn	0741-3106	en_US
dc.identifier.uri	http://dx.doi.org/10.1109/LED.2009.2018493	en_US
dc.identifier.uri	http://hdl.handle.net/11536/7160	-
dc.description.abstract	A new method is proposed and successfully demonstrated for the fabrication of polycrystalline silicon (poly-Si) nanowire (NW) transistors with rectangular-shaped NW channels and two independent gates. The two independently controllable gates allow higher flexibility in device operation and provide a unique insight into the conduction mechanism of the NW device. Our results indicate that dramatic performance enhancement is feasible when the thickness of the NW channel is sufficiently thin, and the two conduction channels in the NW structure are operating simultaneously.	en_US
dc.language.iso	en_US	en_US
dc.subject	Double gate	en_US
dc.subject	nanowire (NW)	en_US
dc.subject	polycrystalline silicon (poly-Si)	en_US
dc.title	Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel Thickness	en_US
dc.type	Article	en_US
dc.identifier.doi	10.1109/LED.2009.2018493	en_US
dc.identifier.journal	IEEE ELECTRON DEVICE LETTERS	en_US
dc.citation.volume	30	en_US
dc.citation.issue	6	en_US
dc.citation.spage	644	en_US
dc.citation.epage	646	en_US
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.identifier.wosnumber	WOS:000266409200021	-
dc.citation.woscount	13	-
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