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dc.contributor.authorChang, Ming-Hungen_US
dc.contributor.authorYang, Zong-Xien_US
dc.contributor.authorHwang, Weien_US
dc.date.accessioned2014-12-08T15:09:28Z-
dc.date.available2014-12-08T15:09:28Z-
dc.date.issued2007en_US
dc.identifier.isbn978-1-4244-0920-4en_US
dc.identifier.issn0271-4302en_US
dc.identifier.urihttp://hdl.handle.net/11536/7235-
dc.identifier.urihttp://dx.doi.org/10.1109/ISCAS.2007.378250en_US
dc.description.abstractAn ADPLL-based frequency synthesizer has been designed and implemented with TSMC 130nm technology model. The cores of it are digital controlled oscillator (DCO) and phase frequency detector (PFD). A modified digitally controlled delay element (DCDE) with characteristics of its monotonicity and insensitivity to PVT variations is presented for the DCO design. A new PFD architecture that can finish phase and frequency comparison and adjustment in one reference cycle is presented. This frequency synthesizer can operate from 300MHz to 1GHz, and achieve frequency acquisition in fifteen reference clock cycles (worst case scenario). The peak-to-peak jitter of the output clock is less than 120ps at 300MRz. Furthermore, the design has been ported to TSMC 100nm process as a reusable IP block verification. The total power dissipation of the ADPLL-based frequency synthesizer is 1.9mW (TSMC 100nm technology) at 1GHz with a 1.2V power supply. With such specifications, it is suitable for high speed clock generation in system-on-a-chip (SoC) applications.en_US
dc.language.isoen_USen_US
dc.titleA 1.9mW portable ADPLL-based frequency synthesizer for high speed clock generationen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/ISCAS.2007.378250en_US
dc.identifier.journal2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11en_US
dc.citation.spage1137en_US
dc.citation.epage1140en_US
dc.contributor.department電子與資訊研究中心zh_TW
dc.contributor.departmentMicroelectronics and Information Systems Research Centeren_US
dc.identifier.wosnumberWOS:000251608401102-
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