單分子層摻雜的研究及其應用

Abstract

現今，當元件微縮到奈米尺寸時將遭遇到許多理論及技術上的挑戰，尤其對材料的摻雜掌控技術更是其中主要的困難之一。在高方向性的鰭狀結構中，傳統的離子佈值技術受限於不均勻的縱向分佈，使得摻雜問題在平面元件即將被立體的3D結構取代的當下將會越來越嚴重。高電子遷移率的鍺或Ⅲ-Ⅴ族材料，也將於下世代技術中引入，然而，離子佈值造成的損傷及後續的高溫製程限制了這些新穎材料的發展。因此，發展新的摻雜方式來解決上述的缺點是急切必要的。 本研究中，我們發展出一個在矽材料表面進行化學分子反應的方式，來形成摻有硼或磷的有機單分子層，並利用其自我組裝的特性來達到均勻性佳，淺摻雜，及無損傷的摻雜過程。此外，自我侷限的反應特性將對摻雜原子分佈有更好的控制能力。因此，這個摻雜方式將能應用到下世代的技術裡。 在特定的熱製程下，兩種類型(硼或磷)摻雜的大約都有數千以上的片電阻值及四個數量級左右的電流比。可以藉由不同機制退火(RTA & MWA)條件或是二次摻雜的方式，將增進上述兩個電性特性。此外，我們也將討論分子摻雜所形成的低摻雜區對三閘極電晶體的影響及製程的簡化方式。 在三閘極元件的表現上，不同退火機制及退火次數將在分別在源/汲區及閘極區造成影響而導致漏電或其他缺點。此外，淺摻雜相對於深摻雜有更好的電特性也會被仔細討論。最後，微波製成將使金屬鎳矽化物的厚度更薄，使得未來有助於引入來降低源/汲極的電阻。

Nowadays, scaling device down to nanometer-size encounter many fundamental and technological challenges, one of the major challenges is attaining controlled doping of materials. As three-dimension structure is about to replace planar device, it become more critical because conventional implantation is suffer from non-uniform vertical doping profile around a high aspect ratio fin structure. New material such as germanium and Ⅲ-Ⅴelements will bring to next technology node because of higher mobility property. However, the damage from implantation and high temperature fabrication process would limit those material developments. In order to overcome those disadvantages, it is necessary to exploit a new doping method as soon as possible. In this study, we develop a new doping way by a chemical molecular reaction upon silicon surface, and then it will form an organic monolayer which is contained Boron/Phosphorus atoms. It is a self-assemble doping process with conformal, ultra-shallow, and damage-free properties; furthermore, the self-limit quality of molecular reaction can get better controllability of dopant distribution. Therefore, it is more suitable for next technology node. It is about thousands Ω/□ and about 4 orders in Ion/Ioff ratio of both n-type and p-type doping at particular thermal condition. Those performances can exchange by different thermal machines (RTA & MWA) and twice times doping. Using this doping method as an extension in tri-gate MOSFET structure and a simple way to reduce fabrication process are also discussed. At tri-gate device performance, different annealing machines and the thermal process times will affect the dopant distribution and the gate dielectric, resulting in leakage and other disadvantages. Furthermore, shallow junction will have better electrical properties contrast to deeper one is also be discussed in detail. At last, it may reduce the NiSi film thickness by MWA method and can be used to reduce resistance at S/D region in future.