二氧化鉿高介電層之N通道金氧半電晶體氧化層缺陷研究

Abstract

隨著CMOS元件快速的微縮,以二氧化矽為基底的閘極介電質因其閘極漏電流過高，不再滿足低功率操作的要求。高介電係數絕緣層可以較厚的物理厚度進而減少閘極漏電並維持相同的電性厚度(EOT) ，因此以高介電係數材料取代二氧化矽是一個重要的議題。與傳統二氧化矽或氮氧化矽相比，以鉿作為閘極介質材料由於存在大量的天生缺陷，在操作下會造成電壓不穩定的嚴重可靠性問題，而這些缺陷分佈在高介電質材料中的不同的能量位置，並對於不同操作條件下有不同反應，因此了解這些缺陷的特性是重要的。

在本論文中，我們首先探討HfO2 nMOS元件中臨界電壓在正偏壓溫度不穩定下(PBTI)的漂移，此漂移由快及慢的電荷捕捉模式貢獻而成，而慢的電荷捕捉會隨著溫度的增加造成更大的臨界電壓漂移，基於此原因，我們在同一次的量測中的各個回復階段(Recovery)增加20℃之溫度，接著根據長時間回復理論，我們可以萃取出在HfO2介電質中相對較淺的缺陷能量位置分布。在HfO2 nMOS 元件中我們比較了有氟攙雜及沒有氟攙雜的元件，發現有氟攙雜之元件在經由正偏壓溫度不穩定後所釋出之相對淺層能量的電子密度比沒有氟的元件還大，但在深層能量釋出之電子密度較小。在熱載子伴隨正偏壓溫度加壓實驗中，發現所產生之缺陷在特定溫度範圍中與溫度無相依性。

本論文中，經由反轉模式(Inversion mode)以及累增模式(Accumulation mode)測量閘極電流的隨機電報雜訊(RTN) ，可以萃取出在HfO2介電質中能量更廣之個別缺陷，在累增模式中同時量測閘極、汲極與基板電流可以分離出位在通道上方以及位在汲極上方區域之個別缺陷。

綜言之，藉由本論文中各種不同萃取的方法，使得我們更加了解HfO2介電質中的能量分布位置以及特性。

With the aggressive scaling of CMOS devices, the conventional SiO2-based gate dielectric has no longer been satisfied to meet the demand of low power consumption due to large gate leakage current. High-k insulators can be grown physically thicker for the same equivalent electrical oxide thickness (EOT), therefore offering significant gate leakage reduction, such that the replacement by high permittivity material created a lot of interests. Compared to the conventional SiO2 or SiOxNy gate dielectrics, Hf-based gate dielectrics are well known to suffer from the serious reliability issues of threshold voltage instabilities under long term devices operation due to large density of preexisting traps. These traps distribute in different energy position in high-k dielectric, and response under different operating conditions. As a consequence, it is important to understand the properties of these traps.

In this thesis, we first discuss the threshold voltage shift of HfO2 nMOS devices under PBTI stress. The Vth shift is a contribution of fast and slow charging process. Since the slow charging process is a temperature dependent phenomenon, the higher stress temperatures can induce larger Vth shift. Based on this concept, we can change the measurement temperature with an increment of 20℃ at each recovery stage in a single measurement. And, based on the long-term recovery theory, we may extract the relatively shallow trap energies in HfO2 gate dielectric. The comparison of high-k nMOS devices between fluorinated and control have shown that the fluorinated devices have larger emitted electrons in the shallow traps than the control devices but smaller emitted electrons in deeper traps under recovery phase after PBTI stress. Also, devices under hot carrier associated with PBTI stress show that generated traps are independent of certain temperatures.

In this thesis, gate current RTN measurement under inversion and accumulation mode are used to investigate the wider range of individual defects in HfO2 dielectrics, and simultaneous measurement of gate, drain, and bulk currents under accumulation mode allow us to separate the trap locations over the channel region to that over the drain region.

In short, traps energy distributions extracted by different methods in this thesis can provide better understanding of the HfO2 gate dielectrics.