標題: | A double-issue java processor design for embedded applications |
作者: | Ko, Hou-Jen Tsai, Chun-Jen 資訊工程學系 Department of Computer Science |
公開日期: | 2007 |
摘要: | Java applications for embedded systems are becoming popular today. CLDC/MIDP is the standard application platform for mobile phones while CDC/PBP is the emerging application platform for next generation digital TV set-top boxes. Although software-based Java Virtual Machines (VM) are prevalent, most of these VMs require a host processor running at much higher clock rate than 300MHz to reach reasonable performance. This is beyond the recommended specification of handsets and set-top boxes. In this paper, we have proposed a double-issue java processor for embedded systems. The design is not tied to any host processors and can be used as an efficient binary execution engine for a full Java Runtime Environment implementation. When synthesized on a Virtex IV FPGA (4VFX12FF66-10), the RTL model can reach over 100MHz and consumes less than 22% resources of the device. |
URI: | http://hdl.handle.net/11536/7323 http://dx.doi.org/10.1109/ISCAS.2007.378382 |
ISBN: | 978-1-4244-0920-4 |
ISSN: | 0271-4302 |
DOI: | 10.1109/ISCAS.2007.378382 |
期刊: | 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 |
起始頁: | 3502 |
結束頁: | 3505 |
Appears in Collections: | Conferences Paper |
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