低電壓容錯快取記憶體之低耗能存取延遲最佳化

Abstract

隨著製成縮小使不斷增加的電晶體臨界電壓變異引發SRAM可靠度和變異性的問題，且行動裝置和未來高度整合的系統晶片為了滿足耗能限制，其工作電壓必須下降。然而快取記憶體在低電壓下容易受干擾而不穩定，甚至會錯誤使其無法使用，且記憶體存取的延遲變異度在新製程下的分布又更加分散。所以在目前記憶體已佔據大部分的處理器耗能的情況下，解決可靠度是現今與未來幾年的快取記憶體設計中最大的挑戰。本篇論文提出一個可變延遲時間存取的快取記憶體不僅為了解決低電壓下的容錯問題，並針對變異性做改善，以達到最佳化存取延遲時間來實現優於最差條件(worst-case)的設計原則，使其有更佳的耗能與效能表現。實驗結果顯示，本篇論文所提出的架構在0.5伏特提高14%的工作頻率下，比起最差條件可以縮小11%的平均記憶體存取時間和6%的耗能。或者，可在不增加耗能的狀況下，能有高於最差條件工作頻率20%的表現。

The ever-increasing transistor threshold-voltage (Vth) variation caused by process technologies shrink brings the variability and reliability issues in SRAM cells. To keep power limitations, scaling down the supply voltage is inevitable in mobile devices and future chips. However, caches become susceptible even fail in low voltages, and the distribution of access latencies increases in new technology nodes. To deal with the respectable power of SRAM in modern processors, the memory reliability wall poses a major challenge in cache design nowadays and continues for years to come. This thesis proposes a variable-latency cache not only for fault-tolerant, but aiming at the variability issues. It leverages latency to achieve better-than-worst-case designs for minimizing energy and improving performance. The experimental results show that Elastic cache reduces 11% average-memory-access time and 6% energy consumption when using 14% higher frequency than worst-case design at 0.5V, and can perform 20% faster frequency without energy loss.